AT89C51CC03U-RDRIM Atmel, AT89C51CC03U-RDRIM Datasheet
AT89C51CC03U-RDRIM
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AT89C51CC03U-RDRIM Summary of contents
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Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 2048 Bytes of On-chip ERAM • 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip ...
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On-chip Emulation Logic (Enhanced Hook System) • Power Saving Modes – Idle Mode – Power-down Mode • Power Supply: 3 volts to 5.5 volts • Temperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C) • Packages: VQFP44, PLCC44, ...
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Pin Configuration 4182E–CAN–05/04 P1.4/AN4/CEX1 7 P1.5/AN5/CEX2 8 P1.6/AN6/CEX3 9 P1.7/AN7/CEX4 P3.0/RxD 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.4/AN4/CEX1 1 P1.5/AN5/CEX2 2 P1.6/AN6/CEX3 3 P1.7/AN7/CEX4 4 ...
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AT89C51CC03 P1.4/AN4/CEX1 8 P1.5/AN5/CEX2 9 P1.6/AN6/CEX3 10 P1.7/AN7/CEX4 PLCC52 P3.0/RxD 14 P4.3/SCK 15 P3.1/TxD 16 P3.2/INT0 17 P3.3/INT1 18 P3.4/T0 19 P3.5/T1/ ...
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CA-BGA64 Top View 4182E–CAN–05/ P1.4/AN4 P1.2/AN2 P1.0/AN0 B P1.5/AN5 P1.3/AN3 P1.1/AN1 C P1.7/AN7 NC P1.6/AN6 D EA P4.3/SCK NC E P3.0 P3 P3.2 P3 P3.5 P4.0 P3.4 H P3.7 P2.7 P3.6 AT89C51CC03 ...
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Pin Name Type Description VSS GND Circuit ground TESTI I Must be connected to VSS VCC Supply Voltage VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 8-bit open drain bi-directional I/O port. ...
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Pin Name Type Description P3.0:7 I/O Port 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs ...
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Pin Name Type Description Reset: RESET I/O A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to ...
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Port 0 and Port 2 4182E–CAN–05/04 Figure 1. Port 1, Port 3 and Port 4 Structure READ LATCH INTERNAL D P1.X Q BUS P3.X P4.X WRITE LATCH CL TO LATCH READ PIN Note: The internal pull-up can be disabled on ...
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Read-Modify-Write Instructions AT89C51CC03 10 Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL READ LATCH INTERNAL BUS D Q P2.X LATCH WRITE TO LATCH READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data ...
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Quasi-Bidirectional Port Operation 4182E–CAN–05/04 write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For ...
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SFR Mapping Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte DPL 82h LSB of DPTR Data Pointer High byte DPH 83h MSB of DPTR Mnemonic ...
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Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WatchDog Timer WDTRST A6h Reset WatchDog Timer WDTPRG A7h Program Mnemonic Add Name ...
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Mnemonic Add Name Interrupt Enable IEN0 A8h Control 0 Interrupt Enable IEN1 E8h Control 1 Interrupt Priority IPL0 B8h Control Low 0 Interrupt Priority IPH0 B7h Control High 0 Interrupt Priority IPL1 F8h Control Low 1 Interrupt Priority IPH1 F7h ...
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Mnemonic Add Name CAN Interrupt CANIE2 C3h Enable Channel byte 2 CAN Status CANSIT1 BAh Interrupt Channel byte1 CAN Status CANSIT2 BBh Interrupt Channel byte2 CAN Timer CANTCON A1h Control CANTIMH ADh CAN Timer high CANTIML ACh CAN Timer low ...
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Mnemonic Add Name CAN Identifier Tag byte 4(PartA) CANIDT4 BFh CAN Identifier Tag byte 4(PartB) CAN Identifier Mask byte 1(PartA) CANIDM1 C4h CAN Identifier Mask byte 1(PartB) CAN Identifier Mask byte 2(PartA) CANIDM2 C5h CAN Identifier Mask byte 2(PartB) CAN ...
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Table 1. SFR Mapping (2) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 00xx x000 PSW FCON D0h 0000 ...
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Clock Description AT89C51CC03 18 The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption ...
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Figure 5. Clock CPU Generation Diagram Hardware byte XTAL1 XTAL2 PD PCON.1 ÷ 2 ÷ CKCON.0 SPIX2 CANX2 CKCON1.0 CKCON0.7 4182E–CAN–05/04 X2B PCON.0 On RESET IDL X2 CKCON.0 ÷ ÷ 2 ÷ 2 ...
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Figure 6. Mode Switching Waveforms XTAL2 X2 bit CPU STD Mode Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference ...
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Registers 4182E–CAN–05/04 Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register CANX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description (1) CAN clock 7 CANX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select ...
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AT89C51CC03 22 Table 3. CKCON1 Register CKCON1 (S:9Fh) Clock Control Register Bit Bit Number Mnemonic Description Reserved 7-1 - The value read from these bits is indeterminate. Do not set these bits. (1) SPI clock Clear ...
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Data Memory 4182E–CAN–05/04 The AT89C51CC03 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 2048 ...
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Internal Space Lower 128 Bytes RAM Upper 128 Bytes RAM Expanded RAM AT89C51CC03 24 The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes ...
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External Space Memory Interface External Bus Cycles 4182E–CAN–05/04 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 10 shows the structure of the external ...
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AT89C51CC03 26 Figure 11. External Data Read Waveforms CPU Clock ALE RD#1 P0 DPL Notes: 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR ...
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Dual Data Pointer Description Application 4182E–CAN–05/04 The AT89C51CC03 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the ...
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Registers AT89C51CC03 28 Table 6. PSW Register PSW (S:8Eh) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 ...
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Bit Bit Number Mnemonic Description ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 4-2 XRS1-0 011 1024 Bytes 100 1792 Bytes 101 2048 Bytes (default configuration after ...
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Power Monitor Description Figure 14. Power Monitor Block Diagram AT89C51CC03 30 The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power sup- ply falls below ...
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Figure 15. Power Fail Detect Vcc Reset Vcc 4182E–CAN–05/04 When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the ...
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Reset Introduction Reset Input AT89C51CC03 32 The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 16. Reset Schematic Power Monitor Hardware Watchdog PCA Watchdog RST The Reset input can be used to force a ...
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Reset Output 4182E–CAN–05/04 As detailed in Section “Watchdog Timer”, page 82, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor ...
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Power Management Introduction Idle Mode Entering Idle Mode Exiting Idle Mode Power-Down Mode AT89C51CC03 34 Two power reduction modes are implemented in the AT89C51CC03. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In ...
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Entering Power-Down Mode Exiting Power-Down Mode Figure 19. Power-Down Exit Waveform Using INT1:0# INT1:0# OSC Active phase 4182E–CAN–05/04 To enter Power-Down mode, set PD bit in PCON register. The AT89C51CC03 enters the Power-Down mode upon execution of the instruction that ...
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AT89C51CC03 36 Table 9. Pin Conditions in Special Operating Modes Mode Port 0 Port 1 Reset Floating High Idle (internal Data Data code) Idle (external Floating Data code) Power- Down(inter Data Data nal code) Power- Down Floating Data (external code) ...
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Registers 4182E–CAN–05/04 Table 10. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-4 - The value read from these bits is indeterminate. Do not set these bits. General Purpose ...
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EEPROM Data Memory Write Data in the Column Latches Programming Read Data AT89C51CC03 38 The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in ...
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Examples 4182E–CAN–05/04 ;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM space ...
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Registers AT89C51CC03 40 Table 11. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. ...
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Program/Code Memory 4182E–CAN–05/04 The AT89C51CC03 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- ...
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External Code Memory Access Memory Interface External Bus Cycles AT89C51CC03 42 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 21 shows the structure of ...
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Figure 22. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 P2 PCH Flash Memory Architecture Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode) Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 4182E–CAN–05/04 PCL ...
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Figure 24. Flash Memory Architecture with ENBOOT=0 (user modemode) Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) AT89C51CC03 44 FFFFh 64K Bytes F800h FM0 0000h Memory space not accessible FFFFh 2K Bytes Flash memory boot space ...
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FM0 Memory Architecture User Space Extra Row (XRow) Hardware security Byte (HSB) Column Latches Cross Flash Memory Access Description 4182E–CAN–05/04 The Flash memory is made blocks (see Figure 23): • The memory array (user space) 64K Bytes ...
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AT89C51CC03 46 Cross Flash Memory Access Action Read Load column latch FM0 (user Flash) Write Read Load column latch FM1 (boot Flash) Write Read External Load column latch memory Write (a) Depend upon general lock bit configuration. ...
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Overview of FM0 Operations Flash Registers (SFR) FCON Register 4182E–CAN–05/04 The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA ...
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FSTA Register Mapping of the Memory Space By default, the user space is accessed by MOVC A, @DPTR instruction for read only. Launching Programming AT89C51CC03 48 Table 14. FSTA Register FSTA Register (S:D3h) Flash Status Register Bit ...
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Status of the Flash Memory Selecting FM1 Loading the Column Latches 4182E–CAN–05/04 Table 16. Programming Spaces Write to FCON FPL3:0 FPS User Extra Row Hardware 5 X Security A X Byte Reset ...
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AT89C51CC03 50 order. The page address of the last address loaded in the column latches will be used for the whole page. When programming is launched, an automatic erase of the locations loaded in the col- umn latches is first ...
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Programming the Flash Spaces User Extra Row 4182E–CAN–05/04 Figure 25. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is used ...
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Hardware Security Byte AT89C51CC03 52 Figure 26. Flash and Extra Row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 27: • Set FPS and map Hardware byte (FCON = 0x0C) • Save ...
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Reset the Column Latches Error Reports Flash Programming Sequence Errors 4182E–CAN–05/04 Figure 27. Hardware Programming Procedure Flash Spaces Programming Save and Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, ...
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Power Down Request Reading the Flash Spaces User Extra Row Hardware Security Byte Flash Protection from Parallel Programming AT89C51CC03 54 Before entering in Power Down (Set bit PD in PCON register) the user should check that no write sequence is ...
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Table 17. Program Lock Bit Program Lock Bits Security LB0 LB1 LB2 level Protection Description program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal ...
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Operation Cross Memory Access Table 18. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write External Read memory Write or Code Roll Over AT89C51CC03 56 Space addressable in read and write are: • RAM ...
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Sharing Instructions 4182E–CAN–05/04 Table 19. Instructions shared XRAM EEPROM Action RAM ERAM Read MOV MOVX Write MOV MOVX Note using Column Latch Table 20. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register ...
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Table 22. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 FMOD0 From FM0 From FM1 (ENBOOT = External code : X 0 EA=0 ...
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... This In-System Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel provide to the customer also all the needed Appli- cation-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory. ...
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Hardware Boot Process AT89C51CC03 60 Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. ...
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... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are describe in an documentation: "In-System Programing: Flash Library for AT89C51CC03" available on the Atmel web site. Table 23. XROW Mapping Description Copy of the Manufacturer Code ...
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Hardware Security Byte AT89C51CC03 62 Table 24. Hardware Security Byte X2B BLJB - Bit Bit Number Mnemonic Description X2 Bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 ...
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Serial I/O Port Figure 31. Serial I/O Port Block Diagram TXD RXD Framing Error Detection Figure 32. Framing Error Block Diagram 4182E–CAN–05/04 The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both ...
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Automatic Address Recognition AT89C51CC03 64 Figure 33. UART Timing in Mode 1 RXD D0 Start bit RI SMOD0=X FE SMOD0=1 Figure 34. UART Timing in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 ...
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Given Address Broadcast Address 4182E–CAN–05/04 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care ...
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Registers AT89C51CC03 66 For slaves A and B, bit don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves ...
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Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register – – – Bit Bit Number Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 27. SADDR ...
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AT89C51CC03 68 Table 29. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 – Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...
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Timers/Counters Timer/Counter Operations Timer 0 4182E–CAN–05/04 The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event ...
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Mode 0 (13-bit Timer) Figure 35. Timer/Counter Mode 0 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 36. Timer/Counter x ...
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Mode 2 (8-bit Timer with Auto- Reload) Figure 37. Timer/Counter Mode 2 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 3 (Two 8-bit Timers) ...
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Timr 1 Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) AT89C51CC03 72 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol- ...
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Interrupt Registers 4182E–CAN–05/04 Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled ...
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AT89C51CC03 74 Table 31. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. ...
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Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 33. TL0 Register TL0 (S:8Ah) ...
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AT89C51CC03 76 Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b – ...
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Timer 2 Auto-Reload Mode Figure 40. Auto-Reload Mode Up/Down Counter see section “Clock” FT2 CLOCK T2 4182E–CAN–05/04 The AT89C51CC03 timer 2 is compatible with timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two ...
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Programmable Clock- Output Figure 41. Clock-Out Mode FT2 CLOCK T2 T2EX AT89C51CC03 78 In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (See Figure 41). The input clock increments TL2 at frequency F repeatedly counts to ...
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Registers 4182E–CAN–05/04 Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 Must ...
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AT89C51CC03 80 Table 37. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 40. RCAP2H ...
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Watchdog Timer Figure 42. Watchdog Timer RESET Fwd Clock - AT89C51CC03 82 AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has ...
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Watchdog Programming 4182E–CAN–05/04 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42. Machine Cycle Count ...
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Watchdog Timer During Power-down Mode and Idle Register AT89C51CC03 84 In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of ...
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Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register – – – Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is used ...
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CAN Controller CAN Controller Description Figure 43. CAN Controller Block Diagram TxDC RxDC AT89C51CC03 86 The CAN Controller provides all the features required to implement the serial communi- cation protocol CAN as defined by BOSCH GmbH. The CAN specification as ...
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CAN Controller Mailbox and Registers Organization Figure 44. CAN Controller Memory Organization SFR’s General Control General Status General Interrupt Bit Timing - 1 Bit Timing - 2 Bit Timing - 3 Enable message object - 1 Enable message object - ...
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Working on Message Objects CAN Controller Management AT89C51CC03 88 The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected ...
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Buffer Mode 4182E–CAN–05/04 Any message object can be used to define one buffer, including non-consecutive mes- sage objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized ...
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IT CAN Management Figure 46. CAN Controller Interrupt Structure CANGIE.5 ENRX RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANSTCH.4 SERR i CANSTCH.3 CERR i CANSTCH.2 FERR i CANSTCH.1 AERR i CANSTCH.0 OVRBUF CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 ...
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Bit Timing and Baud Rate Figure 47. Sample And Transmission Point FCAN Prescaler BRP CLOCK 4182E–CAN–05/04 • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable interrupt on error, ENERCH. To ...
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Figure 48. General Structure of a Bit Period oscillator system clock data (1) Phase error ≤ 0 (2) Phase error ≥ 0 (3) Phase error > 0 (4) Phase error < 0 AT89C51CC03 92 1/ Fcan Bit Rate Prescaler Tscl ...
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Fault Confinement 4182E–CAN–05/04 With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes part in bus communication and can send ...
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Acceptance Filter AT89C51CC03 94 Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 ...
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Data and Remote Frame message object in transmission message object stay in transmission message object in transmission message object in reception by CAN controller message object stay in reception message object in transmission message object in reception by CAN controller ...
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Time Trigger Communication (TTC) and Message Stamping Figure 51. Block Diagram of CAN Timer Fcan ÷ 6 CLOCK TXOK i CANSTCH.4 RXOK i CANSTCH.5 CANSTMPH and CANSTMPL AT89C51CC03 96 The AT89C51CC03 has a programmable 16-bit Timer (CANTIMH and CANTIML) for ...
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CAN Autobaud and Listening Mode Routines Examples 4182E–CAN–05/04 To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledg- ing the received ...
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AT89C51CC03 98 // Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11-bit identi- fier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on ...
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Interrupt routine // Save the current CANPAGE // Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt ...
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CAN SFR’s Table 47. CAN SFR’s With Reset Values (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00xx xx00 00xx ...
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Registers 4182E–CAN–05/04 Table 48. CANGCON Register CANGCON (S:ABh) CAN General Control Register ABRQ OVRQ TTC Bit Number Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control 7 ABRQ ...
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AT89C51CC03 102 Table 49. CANGSTA Register CANGSTA (S:AAh) CAN General Status Register OVFG - Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this bit. Overload ...
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Table 50. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt CANIT - OVRTIM Bit Number Bit Mnemonic Description General Interrupt Flag This status bit is the image of all the CAN controller interrupts sent to the 7 ...
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AT89C51CC03 104 Table 51. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter TEC7 TEC6 TEC5 Bit Number Bit Mnemonic Description Transmit Error Counter 7-0 TEC7:0 see Figure 49 Reset Value = 00h Table 52. CANREC ...
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Table 53. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable ENRX Bit Number Bit Mnemonic Description Reserved 7-6 - The values read from these bits are indeterminate. Do not set these bits. Enable Receive ...
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AT89C51CC03 106 Table 54. CANEN1 Register CANEN1 (S:CEh Read Only) CAN Enable Message Object Registers ENCH14 ENCH13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not ...
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Table 56. CANSIT1 Register CANSIT1 (S:BAh) CAN Status Interrupt Message Object Registers SIT14 SIT13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this ...
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AT89C51CC03 108 Table 58. CANIE1 Register CANIE1 (S:C2h) CAN Enable Interrupt Message Object Registers IECH14 IECH13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set ...
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Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers BRP 5 BRP 4 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...
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AT89C51CC03 110 Table 61. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers SJW 1 SJW 0 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set ...
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Table 62. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers PHS2 2 PHS2 1 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...
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AT89C51CC03 112 Table 63. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register CHNB 3 CHNB 2 CHNB 1 Bit Number Bit Mnemonic Description Selection of Message Object Number 7-4 CHNB3:0 The available numbers are ...
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Table 65. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register DLCW TXOK RXOK Bit Number Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame 7 ...
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AT89C51CC03 114 Table 66. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers IDT 10 IDT 9 IDT 8 Bit Number Bit Mnemonic Description IDentifier tag value 7-0 IDT10:3 ...
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Table 69. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these bits ...
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AT89C51CC03 116 Table 72. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers IDT 12 IDT 11 IDT 10 Bit Number Bit Mnemonic Description IDentifier Tag Value 7-0 IDT12:5 ...
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Table 75. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers IDMSK 2 IDMSK 1 IDMSK 0 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...
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AT89C51CC03 118 Table 77. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these ...
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Table 79. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers IDMSK 20 IDMSK 19 IDMSK 18 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...
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AT89C51CC03 120 Table 81. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers IDMSK 4 IDMSK 3 IDMSK 2 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - ...
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Table 83. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl TPRESC 7 TPRESC 6 TPRESC 5 Bit Number Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter ...
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AT89C51CC03 122 Table 86. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High TIMSTMP TIMSTMP TIMSTMP Bit Number Bit Mnemonic Description TIMSTMP15: High byte of Time Stamp 7-0 8 See Figure 51. No ...
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Table 89. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low TIMTTC 7 TIMTTC 6 TIMTTC 5 Bit Number Bit Mnemonic Description Low byte of TTC Timer 7-0 TIMTTC7:0 See Figure 51. Reset Value = ...
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Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51CC03 124 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU ...
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Baud Rate 4182E–CAN–05/ Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level ...
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Functional Description Figure 54. SPI Module Block Diagram SPSCR SPIF - OVR SPCON SPR2 SPEN SSDIS Operating Modes AT89C51CC03 126 Figure 54 shows a detailed structure of the SPI Module. Internal Bus MODF SPTE UARTM SPTEIE MODFIE SPI Control MSTR ...
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Master Mode Slave Mode Transmission Formats 4182E–CAN–05/04 When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission ...
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Figure 56. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 57. Data Transmission Format (CPHA = 1) ...
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Figure 59. Queuing Transmission In Master Mode SCK MSB B6 B5 MOSI MSB B6 B5 MISO Data Byte 1 BYTE 1 under transmission SPTE 4182E–CAN–05/04 When a transmission is in progress a new data can be queued and sent as ...
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Error Conditions Mode Fault Error (MODF) AT89C51CC03 130 The following flags in the SPSCR register indicate the SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with ...
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OverRun Condition Interrupts 4182E–CAN–05/04 Figure 61. Mode Fault Conditions in Slave Mode 0 SCK cycle # 1 SCK z 0 (from master) 1 MOSI z (from master MISO MSB z (from slave (slave) 0 ...
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Registers Serial Peripheral Control Register (SPCON) AT89C51CC03 132 Figure 62. SPI Interrupt Requests Generation SPIF SPTEIE SPTE MODFIE MODF Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs. ...
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Serial Peripheral Status Register and Control (SPSCR) 4182E–CAN–05/04 Bit Number Bit Mnemonic Description Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. Clock ...
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AT89C51CC03 134 Bit Bit Number Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading SPSCR 4 MODF When ...
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Programmable Counter Array (PCA) PCA Timer 4182E–CAN–05/04 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves ...
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Figure 63. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle PCA Modules AT89C51CC03 136 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit ...
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PCA Interrupt Figure 64. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 PCA Capture Mode 4182E–CAN–05/04 Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...
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Figure 65. PCA Capture Mode CEXn 16-bit Software Timer Mode Figure 66. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to ...
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High Speed Output Mode Figure 67. PCA High Speed Output Mode Write to CCAPnH Reset Write to CCAPnL “0” “1” Enable Pulse Width Modulator Mode 4182E–CAN–05/04 In this mode the CEX output (on port 1) associated with the PCA module ...
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Figure 68. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) PCA WatchDog Timer AT89C51CC03 140 CCAPnH CCAPnL 8-Bit Comparator ECOMn CCAPMn.6 CCAPMn.1 An on-board WatchDog timer is available with the ...
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PCA Registers 4182E–CAN–05/04 Table 94. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL WDTE - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle mode. ...
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AT89C51CC03 142 Table 95. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA ...
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Table 96. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 Bit Bit Number Mnemonic Description CCAPnH 7:0 High ...
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AT89C51CC03 144 Table 98. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read ...
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Table 99. CH Register CH (S:F9h) PCA Counter Register High Value Bit Bit Number Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 100. ...
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Analog-to-Digital Converter (ADC) Features ADC Port1 I/O Functions AT89C51CC03 146 ction de scribe s the on -chip 10 bit an alog -to-d ig ita l c onv erte AT89C51CC03. Eight ADC channels are ...
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Figure 69. ADC Description ADC CLOCK AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 SCH2 SCH1 ADCON.2 ADCON.1 Figure 70. Timing Diagram CLK ADEN T SETUP ADSST ADEOC Note: Tsetup min = ...
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ADC Converter Operation Voltage Conversion Clock Selection Figure 71. A/D Converter clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode AT89C51CC03 148 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the ...
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IT ADC Management Routines examples 4182E–CAN–05/04 An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 72. ADC Interrupt Structure ...
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Registers AT89C51CC03 150 Table 102. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 7-0 CH 0:7 Set to use P1.x as ADC input. Clear to use ...
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Table 104. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler 4-0 ...
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AT89C51CC03 152 Bit Bit Number Mnemonic Description Reserved 7-2 - The value read from these bits are indeterminate. Do not set these bits. ADC result 1-0 ADAT1:0 bits 1-0 Reset Value = 00h 4182E–CAN–05/04 ...
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Interrupt System Introduction Figure 73. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:5 PCA TxD UART RxD Timer 2 TxDC CAN controller RxDC AIN1:0 Converter CAN Timer SPI Controller ...
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AT89C51CC03 154 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all ...
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Registers 4182E–CAN–05/04 Table 109. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, ...
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AT89C51CC03 156 Table 110. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 ...
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Table 111. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority ...
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AT89C51CC03 158 Table 112. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 113. IPL0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...
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AT89C51CC03 160 Table 114. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias industrial........................................................-40°C to 85° automotive..................................................-40°C to +125°C Voltage on V from V ......................................-0. Voltage on Any Pin from V ..................... -0. ...
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Table 115. DC Parameters in Standard Voltage (Continued) Symbol Parameter Power-down Current Industrial I PD Power-down Current Automotive Power Supply Current Industrial I CC Power Supply Current Automotive Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 ...
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DC Parameters for A/D Converter 4182E–CAN–05/04 Figure 75. I Test Condition, Idle Mode CC V RST (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 76. I Test Condition, Power-Down Mode RST EA XTAL2 ...
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AC Parameters Explanation of the AC Symbols AT89C51CC03 164 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or ...
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External Program Memory Characteristics 4182E–CAN–05/04 Table 117. Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ...
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External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 AT89C51CC03 166 Table 119. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV ...
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External Data Memory Characteristics 4182E–CAN–05/04 Table 120. Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ ...
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AT89C51CC03 168 Table 122. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T Max LLDV T Max AVDV T Min LLWL T Max LLWL T ...
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External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing – Shift Register Mode 4182E–CAN–05/04 T LLWL ...
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Shift Register Timing Waveforms INSTRUCTION ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA External Clock Drive Characteristics (XTAL1) AT89C51CC03 170 Table 124. AC Parameters for a Fix Clock ( MHz) Symbol T XLXL T QVHX T XHQX ...
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External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms 4182E–CAN–05/04 V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made at ...
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Clock Waveforms STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST ...
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Flash Memory 4182E–CAN–05/04 Table 127. Timing Symbol Definitions Signals S (Hardware PSEN#,EA condition) R RST B FBUSY flag Table 128. Memory AC Timing VDD = 3V to 5.5V -40 to +85°C Symbol Parameter T Input PSEN# Valid to ...
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... UART AT89C51CC03C-7CTIM CAN AT89C51CC03C-RLTIM CAN AT89C51CC03C-SLSIM CAN AT89C51CC03U-RDTIM UART AT89C51CC03U-S3SIM UART AT89C51CC03C-RDTIM CAN AT89C51CC03C-S3SIM CAN AT89C51CC03U-RLTAM UART AT89C51CC03U-RLTAM CAN AT89C51CC03U-RDTAM UART AT89C51CC03C-RDTAM CAN Datasheet Change Log Changes from 4182B - 09/03 to 4182C 12/03 Changes from 4182C - 12/03 to 4182D 01/04 Changes from 4182D - ...
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Package Drawing CA-BGA 4182E–CAN–05/04 AT89C51CC03 175 ...
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VQFP44 AT89C51CC03 176 4182E–CAN–05/04 ...
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PLCC44 4182E–CAN–05/04 AT89C51CC03 177 ...
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VQFP64 AT89C51CC03 178 4182E–CAN–05/04 ...
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PLCC52 4182E–CAN–05/04 AT89C51CC03 179 ...
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Table of Contents AT89C51CC03 i Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 2 Pin Configuration .................................................................................. 3 CA-BGA64 Top View ............................................................................................5 I/O Configurations................................................................................................. 8 Port 1, Port 3 and Port 4 ....................................................................................... 8 Port 0 and Port 2................................................................................................... ...
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Examples ............................................................................................................ 39 Registers............................................................................................................. 40 Program/Code Memory ...................................................................... 41 External Code Memory Access .......................................................................... 42 Flash Memory Architecture................................................................................. 43 Overview of FM0 Operations .............................................................................. 47 Operation Cross Memory Access ..................................................... 56 Sharing Instructions ........................................................................... 57 In-System Programming (ISP) ........................................................... ...
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AT89C51CC03 iii IT CAN Management .......................................................................................... 90 Bit Timing and Baud Rate ...................................................................................91 Fault Confinement .............................................................................................. 93 Acceptance Filter ................................................................................................ 94 Data and Remote Frame .................................................................................... 95 Time Trigger Communication (TTC) and Message Stamping ............................ 96 CAN Autobaud and Listening ...
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AC Parameters ................................................................................................. 164 Ordering Information ........................................................................ 174 Datasheet Change Log ..................................................................... 174 Changes from 4182B - 09/03 to 4182C 12/03 .................................................. 174 Changes from 4182C - 12/03 to 4182D 01/04.................................................. 174 Package Drawing .............................................................................. 175 CA-BGA ............................................................................................................ 175 ...
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