ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 174
ATMEGA1284P-PU
Manufacturer Part Number
ATMEGA1284P-PU
Description
MCU AVR 128K ISP FLASH 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
4.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-PU
Manufacturer:
LUCENT
Quantity:
32
- ATMEGA644PA-PU PDF datasheet
- ATMEGA644PA-PU PDF datasheet #2
- ATMEGA1284PR231-AU PDF datasheet #3
- ATMEGA1284P-MU PDF datasheet #4
- Current page: 174 of 380
- Download datasheet (7Mb)
17.4.2
17.4.3
8059D–AVR–11/09
Double Speed Operation (U2Xn)
External Clock
Table 17-1.
Some examples of UBRRn values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
Operating Mode
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
194.
f
UBRRn
OSC
Equations for Calculating Baud Rate Register Setting
Figure 17-2 on page 173
System Oscillator clock frequency
Contents of the UBRRHn and UBRRLn Registers, (0-4095)
Equation for Calculating Baud
BAUD
BAUD
BAUD
=
=
=
----------------------------------------- -
16 UBRRn
Rate
-------------------------------------- -
8 UBRRn
-------------------------------------- -
2 UBRRn
for details.
(
(
(
(1)
f
f
f
OSC
OSC
OSC
+
+
+
1
1
1
)
)
)
UBRRn
UBRRn
UBRRn
Equation for Calculating UBRR
ATmega1284P
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
Value
f
f
f
OSC
OSC
OSC
Table 17-9 on
–
–
–
174
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