ATXMEGA64A1-AU Atmel, ATXMEGA64A1-AU Datasheet - Page 15

• Manufacturer Part Number: ATXMEGA64A1-AU
• Description: MCU AVR 64K FLASH 1.6V 100-TQFP
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA64A1-AU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATXMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 78
• Number Of Timers: 8
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 12-bit)
• On-chip Dac: 2 (2-ch x 12-bit)
• Package: 100TQFP
• Device Core: AVR
• Family Name: XMEGA
• Maximum Speed: 32 MHz
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7
8067M–AVR–09/10
ATxmega64A1
ATxmega128A1
ATxmega192A1
ATxmega256A1
ATxmega384A1
ATxmega64A1
ATxmega128A1
ATxmega192A1
ATxmega256A1
ATxmega384A1
Devices
Devices
Flash and EEPROM Page Size
Size (Bytes)
128K + 8K
192K + 8K
256K + 8K
384K + 8K
64K + 4K
Flash
EEPROM
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 15
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) gives the page number and the least significant address bits (FWORD)
gives the word in the page.
Table 7-2.
Table 7-3 on page 15
EEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives
the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3.
Size
2 KB
2 KB
2 KB
4 KB
4 KB
Page Size
(words)
128
256
256
256
256
Number of words and Pages in the Flash.
Number of Bytes and Pages in the EEPROM.
Page Size
FWORD
(Bytes)
Z[7:1]
Z[8:1]
Z[8:1]
Z[8:1]
Z[8:1]
shows the Flash Program Memory organization. Flash write and erase
32
32
32
32
32
shows EEPROM memory organization for the XMEGA A1 devices.
FPAGE
Z[16:8]
Z[17:9]
Z[18:9]
Z[18:9]
Z[19:9]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
E2BYTE
Size (Bytes)
128K
192K
256K
384K
64K
Application
No of Pages
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[11:5]
ADDR[11:5]
E2PAGE
256
256
384
512
768
Size (Bytes)
XMEGA A1
8K
4K
8K
8K
8K
No of Pages
Boot
No of Pages
128
128
64
64
64
16
16
16
16
16
15