PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 70

• Manufacturer Part Number: PIC32MX440F256H-80I/PT
• Description: IC PIC MCU FLASH 256K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F256H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
TABLE 4-2:
4.2.1.1
The POSC has six operating modes, as summarized in
Table 4-3. The first three modes can each be combined
with a PLL module to form the last three modes. Fig-
ures 4-2 through 4-4 show various POSC configura-
tions. The primary oscillator is connected to the OSCI
and OSCO pins of the device family. The primary oscil-
lator can be configured for an external clock input or an
external crystal or resonator.
The XT, XTPLL, HS, and HSPLL modes are External
Crystal or Resonator Controller Oscillator modes. The
XT and HS modes are functionally very similar. The pri-
mary difference is the gain of the internal inverter of the
oscillator circuit (see Figure 4-2). The XT mode is a
medium power, medium frequency mode and has
medium inverter gain. HS mode is higher power and
provides the highest oscillator frequencies and has the
highest inverter gain. OSCO provides crystal/resonator
feedback in both XT and HS Oscillator modes and
hence is not available for use as a input or output in
these modes. The XTPLL and HSPLL modes have a
Phase Locked Loop (PLL) with user selectable input
TABLE 4-3:
DS61143C-page 68
Fast RC Oscillator with PLL Module
(FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
HS
XT
EC
HSPLL
XTPLL
ECPLL
Note: The clock applied to the CPU after applicable prescalers, postscalers, and PLL multipliers must not exceed
Oscillator Mode
2:
3:
4:
the maximum allowable processor frequency.
OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When
the pin is not required by the Oscillator mode it may be configured for one of these options.
Default Oscillator mode for an unprogrammed (erased) device.
When using the PLL modes the input divider must be chosen such that resulting frequency applied to the
PLL is in the range of 4 MHz to 5 MHz.
In this mode, the PLL input divider is forced to ‘2’ to provide a 4 MHz input to the PLL. This parameter
cannot be modified and satisfies the requirements described in Note 3.
Primary Oscillator (POSC)
Oscillator Mode
PRIMARY OSCILLATOR OPERATING MODES
CLOCK SELECTION CONFIGURATION BIT VALUES (CONTINUED)
Description
10 MHz-40 MHz crystal
3.5 MHz-10 MHz resonator
External clock input (0-72 MHz)
10 MHz-40 MHz crystal, PLL enabled
4 MHz-10 MHz resonator, PLL enabled
External clock input (5-72 MHz), PLL enabled
Preliminary
Oscillator
Source
Internal
Internal
divider, multiplier, and output divider to provide a wide
range of output frequencies. The oscillator circuit will
consume more current when the PLL is enabled.
The External Clock modes, EC and ECPLL, allow the
system clock to be derived from an external clock
source. These modes configure the OSCI pin as a
high-impedance input that can be driven by a CMOS
driver. The external clock can be used to drive the sys-
tem clock directly (EC) or the ECPLL module with pres-
cale and postscaler can be used to change the input
clock frequency (ECPLL). The External Clock modes
also disables the internal feedback buffer allowing the
OSCO pin to be used for other functions. In the Exter-
nal Clock mode the OSCO pin can be used as an addi-
tional device I/O pin (see Figure 4-4) or a PBCLK
output pin (see Figure 4-3).
Note:
POSCMD<1:0>
When using the PLL modes the input
divider must be chosen such that resulting
frequency applied to the PLL is in the
range of 4 MHz to 5 MHz.
10
xx
© 2008 Microchip Technology Inc.
FNOSC2:
FNOSC0
001
000
Notes
1,4
1