PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 397
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX460F256L-80IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 397 of 632
- Download datasheet (10Mb)
FIGURE 17-9:
17.2.4.10
This Framed SPI mode is enabled by setting bits
MSTEN
(SPIxCON<31>)
(SPIxCON<30>) to ‘1’. Therefore, both the SCKx and
SSx pins will be inputs. The SSx pin will be sampled on
the sample edge of the SPI clock. When SSx is sam-
pled active, high or low depending on bit, FRMPOL
(SPIxCON<29>), data will be transmitted on the next
transmit edge of SCKx. A connection diagram indicat-
ing signal directions for this operating mode is shown in
Figure 17-10.
The SDO pins is an output and the SCK, SDI and SSx
pins are inputs. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired.
Refer to Table 17-7.
The SDI pin must be configured to properly sample the
data received from the slave device by configuring the
sample bit, SMP (SPIxCON<9>).
Refer to timing diagram shown in Figure 17-7 to deter-
mine the appropriate settings.
17.2.4.11
The following bits must be configured as shown for the
Slave mode of operation when configuring the
SPIxCON register:
• Enable Slave Mode –
• Enable Framed SPI support –
• Select SSx pin as Frame Slave (input) –
© 2008 Microchip Technology Inc.
MSTEN (SPIxCON<5>) = 0
FRMEN (SPIxCON<31>) = 1
FRMSYNC(SPIxCON<30>) = 1
(SPIxCON<5>)
SPI Slave Mode and Frame Slave
Mode
Slave SPIxCON Configuration
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
[SPI Slave, Frame Master]
to
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC32MX3XX/4XX
‘1’,
to
and
‘0’,
FRMSYNC
SDOx
SCKx
SDIx
SSx
FRMEN
Preliminary
Serial Clock
Frame Sync
Pulse
(1)(2)
The remaining bits are shown with example configura-
tions and may be configured as desired:
• Enable module control of SDO pin –
• Configure SCK clock polarity to Idle high –
• Configure SCK clock edge transition from Idle to
• Select SSx active-low pin polarity – FRMPOL
• Select 16-bit data width –
• Sample data input at middle –
• Enable SPI module when CPU Idle –
DISSDO (SPIxCON<12>) = 0
CKP (SPIxCON<6>) = 1
active – CKE (SPIxCON<8>) = 0
(SPIxCON<29>) = 0
MODE<32,16> (SPIxCON<11:10>) = ‘01’
SMP (SPIxCON<9>) = 0
SIDL (SPIxCON<13>) = 0
SDOx
SDIx
SCKx
SSx
[SPI Master, Frame Slave]
PIC32MX3XX/4XX
PROCESSOR 2
DS61143C-page 395
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