PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 292
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX460F256L-80IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 292 of 632
- Download datasheet (10Mb)
PIC32MX3XX/4XX
11.30 Configuring the SOF Threshold
The module counts down the number of bits that could
be transmitted within the current USB full-speed frame.
Since 12,000 bits can be transmitted during the 1 ms
frame time, a counter, not visible to software, is loaded
with the value ‘12,000’ at the start of each frame. The
counter decrements once for each bit time in the frame.
When the counter reaches zero the next frame’s SOF
packet is transmitted, see Figure 11-9.
The SOF threshold register (U1SOF) is used to ensure
that no new tokens are started too close to the end of a
frame. This prevents a conflict with the next frame’s
SOF packet. When the counter reaches the threshold
value of the U1SOF register (the value in the U1SOF
FIGURE 11-9:
Table 11-4 and Table 11-5 show examples of calculat-
ing worst-case bit times.
TABLE 11-4:
DS61143C-page 290
IN
Turnaround
DATA
Turnaround
HANDSHAKE
Inter-packet
Total
Note 1:
Note 1: While the U1SOF register value is described in terms of bytes, these examples show the result in terms
2:
2: In the second table, the IN, DATA, and HANDSHAKE packets are transmitted at low speed (8 times slower
3: These calculations do not take the possibility that the packet data needs to be bit-stuffed for NRZI encoding
Inter-packet delay of 2. An additional 5.5 bit times of latency is added to represent a worst-case propaga-
tion delay through 5 hubs.
Using 64-bytes maximum packet size for this example calculation.
(1)
of bits.
than full speed).
into account.
Note: Drawing is not to scale.
0 ms
Packet
SOF
EXAMPLE OF SOF THRESHOLD CALCULATION: FULL SPEED
ALLOCATION OF BITS FOR A FULL-SPEED FRAME
SYNC, PID, ADDR, ENDP, CRC5, EOP
SYNC, PID, DATA
SYNC, PID, EOP
1 Full-Speed Frame
Preliminary
(2)
, CRC16, EOP
register is in terms of bytes), no new tokens are started
until after the SOF has been transmitted. Thus, the
USB module attempts to ensure that the USB link is idle
when the SOF token needs to be transmitted.
This implies that the value programmed into the
U1SOF register must reserve enough time to insure the
completion of the worst-case transaction. Typically, the
worst-case transaction is an IN token followed by a
maximum-sized data packet from the target, followed
by the response from the host. If the host is targeting a
low-speed device that is bridging through a full-speed
hub, the transaction will also include the special PRE
token packets.
Fields
SOF Threshold
U1SOF * 8
bit times
© 2008 Microchip Technology Inc.
1 ms (12,000 bit times)
SOF
Bits
547
613
35
19
8
2
2
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