PIC16LF877A-I/L Microchip Technology, PIC16LF877A-I/L Datasheet - Page 125

• Manufacturer Part Number: PIC16LF877A-I/L
• Description: IC MCU FLASH 8KX14 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF877A-I/L

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC16LF
• No. Of I/o's: 33
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF877AI/L

10.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit, RCIF
(PIR1<5>), is set. The actual interrupt can be enabled/
disabled
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double-buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then Overrun Error bit, OERR
(RCSTA<1>), is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
TABLE 10-9:
 2003 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
by
by
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
USART SYNCHRONOUS MASTER
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
setting
setting/clearing
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
either
(1)
(1)
ADIE
enable
Bit 6
PEIE
ADIF
RX9
TX9
enable
TMR0IE
SREN
TXEN
RCIF
RCIE
Bit 5
bit,
bit,
SREN
RCIE
CREN
SYNC
INTE
TXIE
Bit 4
TXIF
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIF
RBIE
Bit 3
—
—
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
When setting up a Synchronous Master Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that GIE and PEIE
TMR0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
(bits 7 and 6) of the INTCON register are set.
OERR
TRMT
INTF
Bit 1
RX9D
TX9D
PIC16F87XA
Bit 0
R0IF
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on:
DS39582B-page 123
Value on
all other
Resets