PIC18F4320-I/P Microchip Technology, PIC18F4320-I/P Datasheet - Page 383

• Manufacturer Part Number: PIC18F4320-I/P
• Description: IC MCU FLASH 4KX16 A/D 40-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/P

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams and Specifications ................................ 325
Top-of-Stack Access .......................................................... 54
TRISE Register
TSTFSZ ............................................................................ 296
Two-Speed Start-up ................................................. 237, 247
Two-Word Instructions
TXSTA Register
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Timer0 and Timer1 External Clock .......................... 329
Transition for Entry to SEC_IDLE Mode .................... 34
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 32
Transition for Two-Speed Start-up
Transition for Wake from PRI_IDLE Mode ................. 33
Transition for Wake from RC_RUN Mode
Transition for Wake from SEC_RUN Mode
Transition for Wake from Sleep (HSPLL) ................... 32
Transition to PRI_IDLE Mode .................................... 33
Transition to RC_IDLE Mode ..................................... 35
Transition to RC_RUN Mode ..................................... 37
USART Synchronous Receive
USART Synchronous Reception
USART SynchronousTransmission
A/D Conversion Requirements ................................ 342
Capture/Compare/PWM Requirements ................... 330
CLKO and I/O Requirements ................................... 327
DC Characteristics - Internal RC Accuracy .............. 326
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 325
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements (PIC18F4X20) .... 331
PLL Clock ................................................................. 326
Reset, Watchdog Timer, Oscillator
Timer0 and Timer1 External Clock
USART Synchronous Receive
USART Synchronous Transmission
PSPMODE Bit .......................................................... 109
Example Cases .......................................................... 58
BRGH Bit ................................................................. 198
2
C Bus Data Requirements (Slave Mode) .............. 337
(INTOSC to HSPLL) ......................................... 247
(RC_RUN to PRI_RUN) ..................................... 35
(HSPLL) ............................................................. 34
(Master/Slave) .................................................. 340
(Master Mode, SREN) ...................................... 208
(Master/Slave) .................................................. 340
(Master Mode, CKE = 0) .................................. 332
(Master Mode, CKE = 1) .................................. 333
(Slave Mode, CKE = 0) .................................... 334
(CKE = 1) ......................................................... 335
Requirements ................................................... 338
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ................ 328
Requirements ................................................... 329
Requirements ................................................... 340
Requirements ................................................... 340
2
2
C Bus Data Requirements ................ 339
C Bus Start/Stop Bits
PIC18F2220/2320/4220/4320
U
USART ............................................................................. 195
V
Voltage Reference Specifications .................................... 321
W
Watchdog Timer (WDT) ............................................237, 245
WCOL .............................................................................. 183
WCOL Status Flag ............................................ 183, 185, 188
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 296
XORWF ........................................................................... 297
Asynchronous Mode ................................................ 202
Baud Rate Generator (BRG) ................................... 198
Serial Port Enable (SPEN Bit) ................................. 195
Setting Up 9-bit Mode with Address Detect ............. 204
Synchronous Master Mode ...................................... 206
Synchronous Slave Mode ........................................ 209
Associated Registers ............................................... 246
Control Register ....................................................... 245
During Oscillator Failure .......................................... 248
Programming Considerations .................................. 245
Associated Registers, Receive ........................ 205
Associated Registers, Transmit ....................... 203
Receiver .......................................................... 204
Transmitter ...................................................... 202
Associated Registers ....................................... 198
Baud Rate Formula ......................................... 198
Baud Rates, Asynchronous Mode
Baud Rates, Asynchronous Mode
Baud Rates, Synchronous Mode
High Baud Rate Select (BRGH Bit) ................. 198
Operation in Power Managed Mode ................ 198
Sampling .......................................................... 198
Associated Registers, Reception ..................... 208
Associated Registers, Transmit ....................... 207
Reception ........................................................ 208
Transmission ................................................... 206
Associated Registers, Receive ........................ 210
Associated Registers, Transmit ....................... 209
Reception ........................................................ 210
Transmission ................................................... 209
(BRGH = 0, Low Speed) .......................... 199
(BRGH = 1, High Speed) ......................... 200
(SYNC = 1) .............................................. 201
DS39599C-page 381