DSPIC30F4011-30I/P Microchip Technology, DSPIC30F4011-30I/P Datasheet - Page 124
![IC DSPIC MCU/DSP 48K 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
DSPIC30F4011-30I/P
Manufacturer Part Number
DSPIC30F4011-30I/P
Description
IC DSPIC MCU/DSP 48K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
7.DSPIC30F4011-30IP.pdf
(228 pages)
Specifications of DSPIC30F4011-30I/P
Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F4011-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4011-30I/P
Manufacturer:
CJ
Quantity:
600 000
Part Number:
DSPIC30F4011-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
ATMEL
Quantity:
3 000
Company:
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
MICROCHIP
Quantity:
455
Company:
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4011-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
18.3.4
The Transmit Interrupt Flag (U1TXIF or U2TXIF) is
located in the corresponding interrupt flag register.
The transmitter generates an edge to set the UxTXIF
bit. The condition for generating the interrupt depends
on UTXISEL control bit:
a)
b)
Switching between the two interrupt modes during
operation is possible and sometimes offers more
flexibility.
18.3.5
Setting the UTXBRK bit (UxSTA<11>) will cause the
UxTX line to be driven to logic ‘0’. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be Idle
before setting UTXBRK.
To send a Break character, the UTXBRK bit must be
set by software and must remain set for a minimum of
13 baud clock cycles. The UTXBRK bit is then cleared
by software to generate Stop bits. The user must wait
for a duration of at least one or two baud clock cycles
in order to ensure a valid Stop bit(s) before reloading
the UxTXB or starting other transmitter activity.
Transmission of a Break character does not generate
a transmit interrupt.
18.4
18.4.1
The following steps must be performed while receiving
8-bit or 9-bit data:
1.
2.
3.
4.
5.
DS70135G-page 124
If UTXISEL = 0, an interrupt is generated when a
word is transferred from the transmit buffer to the
Transmit Shift register (UxTSR). This implies that
the transmit buffer has at least one empty word.
If UTXISEL = 1, an interrupt is generated when
a word is transferred from the transmit buffer to
the Transmit Shift register (UxTSR) and the
transmit buffer is empty.
Set up the UART (see
“Transmitting in 8-bit Data
Enable
“Transmitting in 8-bit Data
A receive interrupt will be generated when one
or more data words have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
Read the received data from UxRXREG. The act
of reading UxRXREG will move the next word to
the top of the receive FIFO and the PERR and
FERR values will be updated.
Receiving Data
TRANSMIT INTERRUPT
TRANSMIT BREAK
RECEIVING IN 8-BIT OR 9-BIT DATA
MODE
the
UART
(see
Mode”).
Mode”).
Section 18.3.1
Section 18.3.1
18.4.2
The receive buffer is 4 words deep. Including the
Receive Shift register (UxRSR), the user effectively
has a 5-word deep FIFO buffer.
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0 implies that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read and no
data shift will occur within the FIFO.
The FIFO is reset during any device Reset. It is not
affected when the device enters or wakes up from a
power-saving mode.
18.4.3
The Receive Interrupt Flag (U1RXIF or U2RXIF) can
be read from the corresponding interrupt flag register.
The interrupt flag is set by an edge generated by the
receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
a)
b)
c)
Switching between the interrupt modes during
operation is possible, though generally not advisable
during normal operation.
18.5
18.5.1
The OERR bit (UxSTA<1>) is set if all of the following
conditions occur:
a)
b)
c)
Once OERR is set, no further data is shifted in UxRSR
(until the OERR bit is cleared in software or a Reset
occurs). The data held in UxRSR and UxRXREG
remains valid.
If URXISEL<1:0> = 00 or 01, an interrupt is
generated every time a data word is transferred
from the Receive Shift register (UxRSR) to the
receive buffer. There may be one or more
characters in the receive buffer.
If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive
Shift register (UxRSR) to the receive buffer
which, as a result of the transfer, contains
3 characters.
If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift
register (UxRSR) to the receive buffer which, as
a result of the transfer, contains 4 characters
(i.e., becomes full).
The receive buffer is full.
The Receive Shift register is full, but unable to
transfer the character to the receive buffer.
The Stop bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
Reception Error Handling
RECEIVE BUFFER (U
RECEIVE INTERRUPT
RECEIVE BUFFER OVERRUN
ERROR (OERR BIT)
© 2010 Microchip Technology Inc.
X
RXB)