PIC16F84-04I/P Microchip Technology, PIC16F84-04I/P Datasheet - Page 333
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84-04I/P
Manufacturer Part Number
PIC16F84-04I/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
64 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 333 of 688
- Download datasheet (3Mb)
17.6
17.6.1
1997 Microchip Technology Inc.
Master SSP Module / Basic SSP Module Compatibility
Initialization
Example 17-2:
When changing from the SPI in the Basic SSP module, the SSPSTAT register contains two addi-
tional control bits. These bits are:
• SMP, SPI data input sample phase
• CKE, SPI Clock Edge Select
To be compatible with the SPI of the Master SSP module, these bits must be appropriately con-
figured. If these bits are not at the states shown in
occur.
Table 17-4: New bit States for Compatibility
Basic SSP Module
CLRF
CLRF
BSF
MOVLW
MOVWF
BSF
BSF
BCF
BSF
MOVLW
MOVWF
CKP
1
0
STATUS
SSPSTAT
SSPSTAT, CKE ; CKE = 1
0x31
SSPCON
STATUS, RP0
PIE, SSPIE
STATUS, RP0
INTCON, GIE
DataByte
SSPBUF
SPI Master Mode Initialization
Preliminary
CKP
; Bank 0
; SMP = 0, CKE = 0, and clear status bits
; Set up SPI port, Master mode, CLK/16,
;
;
; Bank 1
; Enable SSP interrupt
; Bank 0
; Enable, enabled interrupts
; Data to be Transmitted
;
; Start Transmission
1
0
Data xmit on falling edge (CKE=1 & CKP=1)
Data sampled in middle (SMP=0 & Master mode)
Could move data from RAM location
Master SSP Module
CKE
0
0
Section 17. MSSP
Table
17-4, improper SPI communication may
SMP
0
0
DS31017A-page 17-57
17
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