PIC16F84-04I/P Microchip Technology, PIC16F84-04I/P Datasheet - Page 165
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84-04I/P
Manufacturer Part Number
PIC16F84-04I/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
64 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 165 of 688
- Download datasheet (3Mb)
10.4
10.5
10.6
PORTD<7:0>
PORTD<7:0>
1997 Microchip Technology Inc.
PSPIF
PSPIF
OBF
OBF
CS
WR
RD
IBF
CS
WR
RD
IBF
Note:
Operation in Sleep Mode
Effect of a Reset
PSP Waveforms
The IBF flag bit is inhibited from being cleared until after this point.
Q1
Q1
When in sleep mode the microprocessor may still read and write the Parallel Slave Port. These
actions will set the PSPIF bit. If the PSP interrupts are enabled, this will wake the processor from
sleep mode so that the PSP data latch may be either read, or written with the next value for the
microprocessor.
After any reset the PSP is disabled and PORTD and PORTE are forced to their default mode.
Figure 10-2
Figure 10-3
Figure 10-2: Parallel Slave Port Write Waveforms
Figure 10-3: Parallel Slave Port Read Waveforms
Q2
Q2
shows the waveform for a read of the PSP by the microprocessor.
shows the waveform for a write from the microprocessor to the PSP, while
Q3
Q3
Section 10. Parallel Slave Port
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
DS31010A-page 10-5
Q4
Q4
10
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