PIC16F84-04I/P Microchip Technology, PIC16F84-04I/P Datasheet - Page 237
![IC MCU FLASH 1KX14 EE 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F84-04I/P
Manufacturer Part Number
PIC16F84-04I/P
Description
IC MCU FLASH 1KX14 EE 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16LF84A-04P.pdf
(125 pages)
3.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16F84-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Operating Supply Voltage
2 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
64 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 237 of 688
- Download datasheet (3Mb)
1997 Microchip Technology Inc.
The SSP module has five registers for I
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
(SSPCON<3:0>) allow one of the following I
• I
• I
• I
• I
• I
Before selecting any I
the appropriate TRIS bits. Selecting an I
and SDA pins to be used as the clock and data lines in I
The SSPSTAT register gives the status of the data transfer. This information includes detection
of a START or STOP bit, specifies if the received byte was data or address, if the next byte is the
completion of 10-bit address, and if this will be a read or write data transfer.
The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register
shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a
doubled buffered receiver. This allows reception of the next byte to begin before reading the last
byte of received data. When the complete byte is received, it is transferred to the SSPBUF reg-
ister and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and the SSPOV bit (SSPCON<6>) is set and the byte
in the SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high
byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of
the address needs to be loaded (A7:A0).
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Firmware controlled Multi-Master mode (start and stop bit interrupts enabled)
C Firmware controlled Multi-Master mode (start and stop bit interrupts enabled)
C Firmware controlled Master mode, slave is idle
2
C mode, the SCL and SDA pins must be programmed to inputs by setting
2
C operation. They are:
2
C mode, by setting the SSPEN bit, enables the SCL
2
C modes to be selected:
2
C operation. Four mode selection bits
Section 15. SSP
2
C mode.
DS31015A-page 15-17
15
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