PIC18F97J60-I/PT Microchip Technology, PIC18F97J60-I/PT Datasheet - Page 359
![IC PIC MCU FLASH 64KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F97J60-I/PT
Manufacturer Part Number
PIC18F97J60-I/PT
Description
IC PIC MCU FLASH 64KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F97J60-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F97J60-I/PT
Manufacturer:
OMRON
Quantity:
3 400
Company:
Part Number:
PIC18F97J60-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
PIC18F97J60-I/PT
Manufacturer:
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Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPT PDF datasheet #7
- Current page: 359 of 480
- Download datasheet (8Mb)
24.4
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
delay, Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
FIGURE 24-3:
© 2009 Microchip Technology Inc.
Two-Speed Start-up
oscillator
Note 1:
CPU Clock
Peripheral
PLL Clock
Program
Counter
INTRC
Output
OSC1
Clock
Wake from Interrupt Event
T
OST
mode
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
= 1024 T
PC
is
OSC
; T
Q1
HS
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
or
Q2
PC + 2
HSPLL
T
OSTS bit Set
PLL
Q3
(1)
Q4
PIC18F97J60 FAMILY
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
24.4.1
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including
Section 3.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS1:SCS0 bit settings, or issue SLEEP instructions,
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
Q1
1
Transition
2
Clock
n-1 n
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
serial
PC + 4
SLEEP
Q2
Q3 Q4
instructions
Q1
PC + 6
DS39762E-page 359
Q2
Q3
(refer
to
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