PIC18F97J60-I/PT Microchip Technology, PIC18F97J60-I/PT Datasheet - Page 236
![IC PIC MCU FLASH 64KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F97J60-I/PT
Manufacturer Part Number
PIC18F97J60-I/PT
Description
IC PIC MCU FLASH 64KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F97J60-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F97J60-I/PT
Manufacturer:
OMRON
Quantity:
3 400
Company:
Part Number:
PIC18F97J60-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F97J60-I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPT PDF datasheet #7
- Current page: 236 of 480
- Download datasheet (8Mb)
PIC18F97J60 FAMILY
REGISTER 18-18: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER
18.4.6
Depending on the application, bits in three of the PHY
module’s registers may also require configuration.
The PDPXMD bit (PHCON1<8>) controls the PHY
half/full-duplex configuration. The application must
program the bit properly, along with the FULDPX bit
(MACON3<0>).
The HDLDIS bit (PHCON2<8>) disables automatic
loopback of data. For proper operation, always set both
HDLDIS and RXAPDIS (PHCON2<4>).
The PHY register, PHLCON (Register 18-13), controls
the outputs of LEDA and LEDB. If an application
requires a LED configuration other than the default,
alter this register to match the new requirements. The
settings
Section 18.1.2 “LED Configuration”.
DS39762E-page 236
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
U-0
—
for
PHY INITIALIZATION SETTINGS
LED
Unimplemented: Read as ‘0’
BBIPG6:BBIPG0: Back-to-Back Inter-Packet Gap Delay Time bits
When FULDPX (MACON3<0>) = 1:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble
times minus 3. The recommended setting is 15h which represents the minimum IEEE specified
Inter-Packet Gap (IPG) of 9.6 μs.
When FULDPX (MACON3<0>) = 0:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble
times minus 6. The recommended setting is 12h which represents the minimum IEEE specified
Inter-Packet Gap (IPG) of 9.6 μs.
BBIPG6
R/W-0
operation
W = Writable bit
‘1’ = Bit is set
BBIPG5
are
R/W-0
discussed
BBIPG4
R/W-0
in
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BBIPG3
R/W-0
18.4.7
There may be circumstances during which the Ethernet
module is not needed for prolonged periods. For exam-
ple, in situations where the application only needs to
transmit or receive Ethernet packets on the occurrence
of a particular event. In these cases, the module can be
selectively powered down.
To selectively disable the module:
1.
2.
3.
4.
Turn off packet reception by clearing the RXEN
bit.
Wait for any in-progress packets to finish being
received
(ESTAT<2>). This bit should be clear before
proceeding.
Wait for any current transmissions to end by
confirming that the TXRTS bit (ECON1<3>) is
clear.
Clear the ETHEN bit. This removes power and
clock sources from the module, and makes the
PHY registers inaccessible. The PHYRDY bit is
also cleared automatically.
DISABLING THE ETHERNET
MODULE
BBIPG2
R/W-0
by
polling
© 2009 Microchip Technology Inc.
x = Bit is unknown
BBIPG1
R/W-0
the
RXBUSY
BBIPG0
R/W-0
bit 0
bit
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