PIC18F97J60-I/PT Microchip Technology, PIC18F97J60-I/PT Datasheet - Page 217
![IC PIC MCU FLASH 64KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F97J60-I/PT
Manufacturer Part Number
PIC18F97J60-I/PT
Description
IC PIC MCU FLASH 64KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F97J60-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F97J60-I/PT
Manufacturer:
OMRON
Quantity:
3 400
Company:
Part Number:
PIC18F97J60-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F97J60-I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPT PDF datasheet #7
- Current page: 217 of 480
- Download datasheet (8Mb)
18.2.2
Like other peripherals, direct control of the Ethernet
module is accomplished through a set of SFRs.
Because of their large number, the majority of these
registers are located in the bottom half of Bank 14 of
the microcontroller’s data memory space.
Five key SFRs for the Ethernet module are located in
the microcontroller’s regular SFR area in Bank 15,
where fast access is possible. They are:
• ECON1
• EDATA
• EIR
• The Ethernet Buffer Read Pointer pair (ERDPTH
ECON1 is described along with other Ethernet control
registers in the following section. EDATA and
ERDPTH:ERDPTL are the Ethernet Data Buffer
registers and its pointers during read operations (see
Section 18.2.1 “Ethernet Buffer and Buffer Pointer
Registers”). EIR is part of the Ethernet interrupt
structure and is described in Section 18.3 “Ethernet
Interrupts”.
REGISTER 18-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
and ERDPTL)
TXRST
R/W-0
SFRs AND THE ETHERNET
MODULE
TXRST: Transmit Logic Reset bit
1 = Transmit logic is held in Reset
0 = Normal operation
RXRST: Receive Logic Reset bit
1 = Receive logic is held in Reset
0 = Normal operation
DMAST: DMA Start and Busy Status bit
1 = DMA copy or checksum operation is in progress (set by software, cleared by hardware or software)
0 = DMA hardware is Idle
CSUMEN: DMA Checksum Enable bit
1 = DMA hardware calculates checksums
0 = DMA hardware copies buffer memory
TXRTS: Transmit Request to Send bit
1 = The transmit logic is attempting to transmit a packet (set by software, cleared by hardware or software)
0 = The transmit logic is Idle
RXEN: Receive Enable bit
1 = Packets which pass the current filter configuration will be written into the receive buffer
0 = All packets received will be discarded by hardware
Unimplemented: Read as ‘0’
RXRST
R/W-0
ECON1: ETHERNET CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
DMAST
R/W-0
CSUMEN
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
TXRTS
R/W-0
Many of the Ethernet SFRs in Bank 14 serve as pointer
registers to indicate addresses within the dedicated
Ethernet buffer for storage and retrieval of packet data.
Others store information for packet pattern masks or
checksum operations. Several are used for controlling
overall module operations, as well as specific MAC and
PHY functions.
18.2.3
The ECON1 register (Register 18-1) is used to control
the main functions of the module. Receive enable, trans-
mit request and DMA control bits are all located here.
The ECON2 register (Register 18-2) is used to control
other top level functions of the module. The ESTAT
register (Register 18-3) is used to report the high-level
status of the module and Ethernet communications.
The Ethernet SFRs with the ‘E’ prefix are always
accessible, regardless of whether or not the module is
enabled.
ETHERNET CONTROL REGISTERS
R/W-0
RXEN
x = Bit is unknown
U-0
—
DS39762E-page 217
U-0
—
bit 0
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