ATMEGA165P-16AU Atmel, ATMEGA165P-16AU Datasheet - Page 87

• Manufacturer Part Number: ATMEGA165P-16AU
• Description: IC AVR MCU 16K 16MHZ 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165P-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.6.1
13.7
13.7.1
13.7.2
8019K–AVR–11/10
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on
the OC0A Register is to be performed on the next compare match. For compare output actions
in the non-PWM modes refer to
on page
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0A strobe bits.
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Out-
put mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at
a compare match.
For detailed timing information refer to
13-10 on page 92
91.
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
94, and for phase correct PWM refer to
See “Register Description” on page 93.
See “Compare Match Output Unit” on page 86.
and
Figure 13-11 on page 92
Table 13-3 on page
Figure 13-8 on page
Table 13-5 on page
in
94. For fast PWM mode, refer to
“Timer/Counter Timing Diagrams” on page
91,
Figure 13-9 on page
94.
ATmega165P
Table 13-4
92,
Figure
87