ATMEGA165P-16AU Atmel, ATMEGA165P-16AU Datasheet - Page 236
![IC AVR MCU 16K 16MHZ 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165P-16AU
Manufacturer Part Number
ATMEGA165P-16AU
Description
IC AVR MCU 16K 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.5.4
8019K–AVR–11/10
Scanning the Analog Comparator
Table 23-1
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Table 23-1.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
nals are described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Figure 23-7. Analog Comparator
Enable Signal
EXTCLKEN
OSCON
OSC32EN
ADCEN
ACME
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
summaries the scan registers for the external clock pin XTAL1, oscillators with
ADC MULTIPLEXER
Scan Signals for the Oscillator
REFERENCE
OUTPUT
BANDGAP
Scanned
Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
Table 23-2 on page
Figure 23-8 on page 237
ACBG
Clock Option
External Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
237.
(1)(2)(3)
is attached to each of these signals. The sig-
ACD
AC_IDLE
ATmega165P
Scanned Clock Line
when not Used
Figure
1
0
1
23-7. The
ACO
236
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