PIC16F84A-20I/SS Microchip Technology, PIC16F84A-20I/SS Datasheet - Page 102
![IC MCU FLASH 1KX14 EE 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F84A-20I/SS
Manufacturer Part Number
PIC16F84A-20I/SS
Description
IC MCU FLASH 1KX14 EE 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84A-20I/SS
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
20MHz
No. Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
13
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
64 B
Height
1.75 mm
Length
7.2 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
5.3 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPI3-DB16F84A - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84A-20I/SS
Manufacturer:
MICROCHIP
Quantity:
2 560
Part Number:
PIC16F84A-20I/SS
Manufacturer:
MIC
Quantity:
20 000
- Current page: 102 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
6.3
6.3.1
6.3.2
DS31006A-page 6-8
General Purpose Registers (GPR)
Special Function Registers (SFR)
Data Memory Organization
Data memory is made up of the Special Function Registers (SFR) area, and the General Pur-
pose Registers (GPR) area. The SFRs control the operation of the device, while GPRs are the
general area for data storage and scratch pad operations.
The data memory is banked for both the GPR and SFR areas. The GPR area is banked to allow
greater than 96 bytes of general purpose RAM to be addressed. SFRs are for the registers that
control the peripheral and core functions. Banking requires the use of control bits for bank selec-
tion. These control bits are located in the STATUS Register (STATUS<7:5>).
one of the data memory map organizations, this organization is device dependent.
To move values from one register to another register, the value must pass through the W register.
This means that for all register-to-register moves, two instruction cycles are required.
The entire data memory can be accessed either directly or indirectly. Direct addressing may
require the use of the RP1:RP0 bits. Indirect addressing requires the use of the File Select Reg-
ister (FSR). Indirect addressing uses the Indirect Register Pointer (IRP) bit of the STATUS regis-
ter for accesses into the Bank0 / Bank1 or the Bank2 / Bank3 areas of data memory.
Some Mid-Range MCU devices have banked memory in the GPR area. GPRs are not initialized
by a Power-on Reset and are unchanged on all other resets.
The register file can be accessed either directly, or using the File Select Register FSR, indirectly.
Some devices have areas that are shared across the data memory banks, so a read / write to
that area will appear as the same location (value) regardless of the current bank. We refer to this
area as the Common RAM.
The SFRs are used by the CPU and Peripheral Modules for controlling the desired operation of
the device. These registers are implemented as static RAM.
The SFRs can be classified into two sets, those associated with the “core” function and those
related to the peripheral functions. Those registers related to the “core” are described in this sec-
tion, while those related to the operation of the peripheral features are described in the section
of that peripheral feature.
All Mid-Range MCU devices have banked memory in the SFR area. Switching between these
banks requires the RP0 and RP1 bits in the STATUS register to be configured for the desired
bank. Some SFRs are initialized by a Power-on Reset and other resets, while other SFRs are
unaffected.
The register file can be accessed either directly, or using the File Select Register FSR, indirectly.
Note:
The Special Function Register (SFR) Area may have General Purpose Registers
(GPRs) mapped in these locations.
1997 Microchip Technology Inc.
Figure 6-5
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