PIC18LF2331-I/SP Microchip Technology, PIC18LF2331-I/SP Datasheet - Page 67
![IC MCU FLASH 4KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2331-I/SP
Manufacturer Part Number
PIC18LF2331-I/SP
Description
IC MCU FLASH 4KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18LF2331-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- Current page: 67 of 392
- Download datasheet (4Mb)
6.5
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a 12-bit
address, allowing up to 4,096 bytes of data memory. The
memory space is divided into as many as 16 banks that
contain 256 bytes each. PIC18F2331/2431/4331/4431
devices implement all 16 banks.
Figure 6-6
PIC18F2331/2431/4331/4431 devices. The data mem-
ory contains Special Function Registers (SFRs) and
General Purpose Registers (GPRs). The SFRs are used
for control and status of the controller and peripheral
functions, while GPRs are used for data storage and
scratchpad operations in the user’s application. Any
read of an unimplemented location will read as ‘0’s.
FIGURE 6-6:
2010 Microchip Technology Inc.
BSR<3:0>
= 0000
= 0001
= 0010
= 0011
= 1110
= 1111
Data Memory Organization
shows the data memory organization for the
DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES
Bank 14
Bank 15
Bank 3
Bank 0
Bank 1
Bank 2
to
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
Data Memory Map
Access RAM
Read ‘00h’
Unused
Unused
GPR
GPR
GPR
SFR
PIC18F2331/2431/4331/4431
000h
05Fh
060h
0FFh
100h
1FFh
200h
2FFh
300h
EFFh
F00h
F5Fh
F60h
FFFh
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
BSR.
detailed description of the Access RAM.
Section 6.5.2 “Access Bank”
When a = 0:
When a = 1:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
General Purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
The BSR specifies the bank
used by the instruction.
Access RAM High
Access RAM Low
Access Bank
(SFRs)
DS39616D-page 67
provides a
00h
5Fh
60h
FFh
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