PIC18LF2331-I/SP Microchip Technology, PIC18LF2331-I/SP Datasheet - Page 300
![IC MCU FLASH 4KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2331-I/SP
Manufacturer Part Number
PIC18LF2331-I/SP
Description
IC MCU FLASH 4KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18LF2331-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- Current page: 300 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39616D-page 300
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
W
Q1
=
=
=
register ‘f’
Complement f
[ label ] COMF
0 f 255
d [0,1]
a [0,1]
(f) dest
N, Z
The contents of register, ‘f’, are comple-
mented. If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored back in
register, ‘f’. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value.
1
1
COMF
Read
0001
Q2
0x13
0x13
0xEC
11da
REG, W
Process
Data
Q3
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC Address
W
REG
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, Skip if f = W
[ label ] CPFSEQ
0 f 255
a [0,1]
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
None
Compares the contents of data memory
location, ‘f’, to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value.
1
1(2)
Note:
HERE
NEQUAL
EQUAL
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
=
=
=
2010 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
HERE
?
?
W;
Address (EQUAL)
W;
Address (NEQUAL)
CPFSEQ REG
:
:
001a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
f [,a]
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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