PIC18LF2331-I/SP Microchip Technology, PIC18LF2331-I/SP Datasheet - Page 207
![IC MCU FLASH 4KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2331-I/SP
Manufacturer Part Number
PIC18LF2331-I/SP
Description
IC MCU FLASH 4KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18LF2331-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- Current page: 207 of 392
- Download datasheet (4Mb)
REGISTER 19-2:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
Note 1:
WCOL
R/W-0
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, these pins must be properly configured as inputs or outputs.
Bit combinations not specifically listed here are either reserved or implemented in I
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control.
1 = Enables clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPOV
2
2
2
R/W-0
C™ mode:
C mode:
C mode:
software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(2)
PIC18F2331/2431/4331/4431
R/W-0
CKP
(1)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
(3)
SSPM2
R/W-0
(3)
x = Bit is unknown
SSPM1
R/W-0
2
C™ mode only.
(3)
DS39616D-page 207
SSPM0
R/W-0
bit 0
(3)
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