PIC24FJ128GA010-I/PT Microchip Technology, PIC24FJ128GA010-I/PT Datasheet - Page 166
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PIC24FJ128GA010-I/PT
Manufacturer Part Number
PIC24FJ128GA010-I/PT
Description
IC PIC MCU FLASH 128K 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ64GA006-IPT.pdf
(240 pages)
3.PIC24FJ64GA006-IPT.pdf
(22 pages)
4.PIC24FJ128GA008-IPT.pdf
(12 pages)
5.PIC24FJ128GA006-IPT.pdf
(231 pages)
6.PIC24FJ128GA010-IPT.pdf
(230 pages)
Specifications of PIC24FJ128GA010-I/PT
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
84
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
No. Of Pwm Channels
5
Embedded Interface Type
EUART, I2C, PSP, SPI
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Package
100TQFP
Device Core
PIC
Family Name
PIC24
Maximum Speed
16 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128GA010-I/PT
Manufacturer:
Microchi
Quantity:
627
Company:
Part Number:
PIC24FJ128GA010-I/PT
Manufacturer:
MICROCHIP
Quantity:
212
Company:
Part Number:
PIC24FJ128GA010-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJ128GA010 FAMILY
18.2
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 3 seconds
per month. This is accomplished by finding the number
of error clock pulses and storing the value into the
lower half of the RCFGCAL register. The 8-bit signed
value loaded into the lower half of RCFGCAL is multi-
plied by four and will be either added or subtracted from
the RTCC timer, once every minute. Refer to the steps
below for RTCC calibration:
1.
2.
EQUATION 18-1:
(Ideal Frequency
3.
4.
DS39747E-page 166
Note:
Using another timer resource on the device, the
user must find the error of the 32.768 kHz
crystal.
Once the error is known, it must be converted to
the number of error clock pulses per minute.
a) If the oscillator is faster then ideal (negative
result form step 2), the RCFGCAL register value
needs to be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter once every minute.
b) If the oscillator is slower then ideal (positive
result from step 2), the RCFGCAL register value
needs to be positive. This causes the specified
number of clock pulses to be subtracted from
the timer counter once every minute.
Divide the number of error clocks per minute by
4 to get the correct CAL value and load the
RCFGCAL register with the correct value. (Each
1-bit increment in CAL adds or subtracts
4 pulses). Load the RCFGCAL register with the
correct value.
Writes to the lower half of the RCFGCAL regis-
ter should only occur when the timer is turned
off, or immediately after the rising edge of the
seconds pulse.
Calibration
It is up to the user to include in the error
value the initial error of the crystal, drift
due to temperature and drift due to crystal
aging.
† Ideal Frequency = 32,768 Hz
†
– Measured Frequency) * 60 = Clocks per Minute
18.3
• Configurable from half second to one year
• Enabled using the ALRMEN bit
• One-time alarm and repeat alarm options available
18.3.1
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVALH:ALRMVALL should only take place when
ALRMEN = 0.
As shown in Figure 18-2, the interval selection of the
alarm is configured
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur. The alarm can also be con-
figured to repeat based on a preconfigured interval.
The amount of times this occurs once the alarm is
enabled is stored in the lower half of the ALCFGRPT
register.
When ALCFGRPT = 00 and the CHIME bit = 0
(ALCFGRPT<14>), the repeat function is disabled and
only a single alarm will occur. The alarm can be
repeated up to 255 times by loading the lower half of
the ALCFGRPT register with FFh.
After each alarm is issued, the ALCFGRPT register is
decremented by one. Once the register has reached
‘00’, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off. Indefinite repetition of the alarm can
occur if the CHIME bit = 1. Instead of the alarm being
disabled when the ALCFGRPT register reaches ‘00’, it
will roll over to FF and continue counting indefinitely
when CHIME = 1.
18.3.2
At every alarm event an interrupt is generated. In addi-
tion, an alarm pulse output is provided that operates at
half the frequency of the alarm. This output is
completely synchronous to the RTCC clock and can be
used as a trigger clock to other peripherals.
(ALCFGRPT<15>, Register 18-3)
Note:
Alarm
CONFIGURING THE ALARM
ALARM INTERRUPT
Changing any of the registers, other then
the RCFGCAL and ALCFGRPT registers
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that the
ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
© 2009 Microchip Technology Inc.
through the AMASK bits