PIC24FJ128GA010-I/PT Microchip Technology, PIC24FJ128GA010-I/PT Datasheet - Page 131

IC PIC MCU FLASH 128K 100TQFP

PIC24FJ128GA010-I/PT

Manufacturer Part Number
PIC24FJ128GA010-I/PT
Description
IC PIC MCU FLASH 128K 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ128GA010-I/PT

Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
84
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
No. Of Pwm Channels
5
Embedded Interface Type
EUART, I2C, PSP, SPI
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Package
100TQFP
Device Core
PIC
Family Name
PIC24
Maximum Speed
16 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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15.0
The Inter-Integrated Circuit (I
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
The I
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I
• Clock stretching to provide delays for the
• Both 100 kHz and 400 kHz bus specifications.
• Configurable address masking
• Multi-Master modes to prevent loss of messages
• Bus Repeater mode, allowing the acceptance of
• Automatic SCL
A block diagram of the module is shown in Figure 15-1.
© 2009 Microchip Technology Inc.
Note:
processor to respond to a slave data request
in arbitration
all messages as a slave regardless of the address
2
C module supports these features:
INTER-INTEGRATED CIRCUIT
(I
2
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 24. “Inter-
Integrated Circuit™ (I
in the “PIC24F Family Reference Manual”
for more information.
C™)
2
C) module is a serial
2
C™)” (DS39702)
2
C protocol
PIC24FJ128GA010 FAMILY
15.1
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for and verify an Acknowledge from the
11. Enable master reception to receive serial
12. Generate an ACK or NACK condition at the end
13. Generate a Stop condition on SDAx and SCLx.
Assert a Start condition on SDAx and SCLx.
Send the I
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the slave with
a read indication.
slave.
memory data.
of a received byte of data.
Communicating as a Master in a
Single Master Environment
2
C device address byte to the slave
DS39747E-page 131

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