DSPIC30F3014-20I/ML Microchip Technology, DSPIC30F3014-20I/ML Datasheet - Page 158

• Manufacturer Part Number: DSPIC30F3014-20I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3014-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301420IML

TABLE 20-7:
TABLE 20-8:
RCON
OSCCON
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR
FGS
FICD
Legend:
Note
File Name
Name
SFR
1:
2:
3:
4:
1:
2:
Addr.
0740
0742
0744
0770
0772
— = unimplemented bit, read as ‘0’
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Reset state depends on type of Reset.
Reset state depends on Configuration bits.
These bits are not available in dsPIC30F3014 devices.
— = unimplemented bit, read as ‘0’
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
F8000C
F80000
F80002
F80004
F8000A
Addr.
IC8MD
T5MD
TRAPR
Bit 15
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
—
—
(4)
(4)
Bits 23-16
IOPUWR
IC7MD
T4MD
—
—
—
—
—
Bit 14
—
(4)
(4)
COSC<2:0>
FWDTEN
MCLREN
Bit 13
BGST LVDEN
T3MD
Bit 15
—
—
FCKSM<1:0>
—
—
Bit 12 Bit 11
T2MD
—
—
Bit 14
—
—
—
—
T1MD
—
—
—
Bit 13
—
—
—
—
—
Bit 10
—
—
—
LVDL<3:0>
Bit 12
NOSC<2:0>
—
—
—
—
—
IC2MD
Bit 9
—
—
(1)
Bit 11
(1)
—
—
—
—
—
DCIMD
IC1MD
Bit 8
—
(4)
Bit 10
—
—
—
—
I2CMD U2MD
EXTR
Bit 7
POST<1:0>
—
—
FOS<2:0>
SWR SWDTEN WDTO
Bit 9
Bit 6
—
—
—
—
—
—
LOCK
U1MD
Bit 8
Bit 5
—
—
—
—
—
—
BOREN
BKBUG
Bit 4
Bit 7
—
—
—
—
—
—
—
OC4MD
SPI1MD
SLEEP
TUN3
Bit 3
CF
Bit 6
COE
—
—
—
—
(4)
OC3MD
Bit 5
FWPSA<1:0>
TUN2
Bit 2
IDLE
BORV<1:0>
—
—
—
—
—
(4)
LPOSCEN OSWEN
Bit 4
OC2MD
—
—
C1MD
TUN1
Bit 1
BOR
Bit 3
—
—
—
ADCMD 0000 0000 0000 0000
OC1MD 0000 0000 0000 0000
TUN0
Bit 0
POR
Reserved
FPR<4:0>
Bit 2
FWPSB<3:0>
—
—
0000 0000 0000 0000
(2)
Reset State
(Note 2)
(Note 3)
Bit 1
FPWRT<1:0>
GCP
ICS<1:0>
GWRP
Bit 0