PIC18F2331-I/SP Microchip Technology, PIC18F2331-I/SP Datasheet - Page 292

• Manufacturer Part Number: PIC18F2331-I/SP
• Description: IC PIC MCU FLASH 4KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39616D-page 292
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG = 0xC7
FLAG_REG = 0x47
Q1
register ‘f’
Bit Clear f
[ label ] BCF
0  f  255
0  b  7
a [0,1]
0  f<b>
None
Bit ‘b’ in register, ‘f’, is cleared. If ‘a’ is
‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1
BCF
Read
1001
Q2
FLAG_REG, 7
bbba
Process
Data
f,b[,a]
Q3
ffff
register ‘f’
Write
Q4
ffff
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Negative
If Negative
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
[ label ] BN
-128  n  127
if Negative bit is ‘1’,
(PC) + 2 + 2n  PC
None
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
‘n’
‘n’
Q2
Q2
=
=
=
=
=
 2010 Microchip Technology Inc.
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
0110
operation
BN
n
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn