AT89C51IC2-RLTIL Atmel, AT89C51IC2-RLTIL Datasheet - Page 91
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AT89C51IC2-RLTIL
Manufacturer Part Number
AT89C51IC2-RLTIL
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51IC2-SLRIM.pdf
(147 pages)
Specifications of AT89C51IC2-RLTIL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
640
Company:
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
4 116
4301D–8051–02/08
SSSTA
Status
Code
08h
10h
18h
20h
28h
30h
38h
Status of the Two-
wire Bus and Two-
wire Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted; ACK has
been received
SLA+W has been
transmitted; NOT ACK
has been received
Data byte has been
transmitted; ACK has
been received
Data byte has been
transmitted; NOT ACK
has been received
Arbitration lost in
SLA+W or data bytes
To/From SSDAT
Write SLA+W
Write SLA+W
Write SLA+R
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Table 68.
Application software response
Status in master transmitter mode
SSSTA
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SSSTO
To SSCON
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by Two-wire Hardware
SLA+W will be transmitted.
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Two-wire bus will be released and not addressed
slave mode will be entered.
A START condition will be transmitted when the bus
becomes free.
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