AT89C51IC2-RLTIL Atmel, AT89C51IC2-RLTIL Datasheet - Page 52
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AT89C51IC2-RLTIL
Manufacturer Part Number
AT89C51IC2-RLTIL
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51IC2-SLRIM.pdf
(147 pages)
Specifications of AT89C51IC2-RLTIL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
640
Company:
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
4 116
52
AT89C51IC2
Table 37. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
FE/SM0
Number
Bit
7
7
6
5
4
3
2
1
0
Mnemonic
SM1
SM0
SM1
SM2
REN
RB8
TB8
Bit
6
FE
RI
TI
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
Serial port Mode bit 1
SM0
0
0
1
1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
o transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 18. and
Figure 19. in the other modes.
SM2
5
SM1
0
1
0
1
REN
Mode
Shift Register F
8-bit UART
9-bit UART
9-bit UART
4
TB8
3
Baud Rate
Variable
F
Variable
XTAL
XTAL
/12 (or F
/64 or F
RB8
2
XTAL
XTAL
/32
/6 in mode X2)
TI
1
4301D–8051–02/08
RI
0