AT89C51IC2-RLTIL Atmel, AT89C51IC2-RLTIL Datasheet - Page 77
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AT89C51IC2-RLTIL
Manufacturer Part Number
AT89C51IC2-RLTIL
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51IC2-SLRIM.pdf
(147 pages)
Specifications of AT89C51IC2-RLTIL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
640
Company:
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
4 116
Registers
Serial Peripheral Control
Register (SPCON)
4301D–8051–02/08
Figure 32. SPI Interrupt Requests Generation
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
•
•
•
•
•
•
Table 58 describes this register and explains the use of each bit
Table 58. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
Bit Number
SPR2
SPIF
MODF
SSDIS
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
7
7
6
5
4
3
2
SPEN
6
Bit Mnemonic
SSDIS
MSTR
SPEN
CPOL
CPHA
SPR2
SPI Transmitter
CPU Interrupt Request
SSDIS
SPI Receiver/error
CPU Interrupt Request
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
MSTR
4
CPOL
3
CPU Interrupt Request
SPI
.
CPHA
2
SPR1
1
SPR0
0
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