PIC24FJ96GA006-I/PT Microchip Technology, PIC24FJ96GA006-I/PT Datasheet - Page 142
![IC PIC MCU FLASH 48KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ96GA006-I/PT
Manufacturer Part Number
PIC24FJ96GA006-I/PT
Description
IC PIC MCU FLASH 48KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.DV164033.pdf
(50 pages)
2.PIC24FJ16GA002-ISS.pdf
(52 pages)
3.PIC24FJ64GA006-IPT.pdf
(240 pages)
4.PIC24FJ64GA006-IPT.pdf
(22 pages)
Specifications of PIC24FJ96GA006-I/PT
Program Memory Type
FLASH
Program Memory Size
96KB (32K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011, DV164033, AC164127, MA240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ96GA006-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DV164033 PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ64GA006-IPT PDF datasheet #3
- PIC24FJ64GA006-IPT PDF datasheet #4
- Current page: 142 of 240
- Download datasheet (4Mb)
PIC24FJ128GA010 FAMILY
REGISTER 16-1:
DS39747E-page 142
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
Note 1:
R/W-0, HC
UARTEN
WAKE
R/W-0
This feature is only available for the 16x BRG mode (BRGH = 0).
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN1:UEN0: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latches
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)
LPBACK
R/W-0
hardware on following rising edge
cleared in hardware upon completion
U-0
—
UxMODE: UARTx MODE REGISTER
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
R/W-0, HC
ABAUD
USIDL
R/W-0
IREN
RXINV
R/W-0
R/W-0
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTSMD
R/W-0
R/W-0
BRGH
PDSEL1
R/W-0
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
PDSEL0
R/W-0
R/W-0
UEN1
STSEL
R/W-0
R/W-0
UEN0
bit 8
bit 0
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