PIC24FJ64GA104-I/PT Microchip Technology, PIC24FJ64GA104-I/PT Datasheet
PIC24FJ64GA104-I/PT
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PIC24FJ64GA104-I/PT Summary of contents
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... PIC24FJ64GA104 Family © 2009 Microchip Technology Inc. 28/44-Pin, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet General Purpose DS39951B ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24FJ64GA104 FAMILY Special Microcontroller Features (continued): • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary • Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip FRC Oscillator • ...
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... PIC24FJ64GA104 FAMILY Peripheral Features: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - available pins (44-pin devices) - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes • 8-Bit Parallel Master Port (PMP/PSP 16-bit multiplexed addressing, with dedicated address pins on 44-pin devices ...
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... Legend: RPn represents remappable peripheral pins. Note 1: Gray shading indicates 5.5V tolerant input pins. 2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. 3: The back pad on QFN devices should be connected to V © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY AN11/C1INC/RP13/CN13/PMRD/REFO/RB13 ...
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... PIC24FJ64GA104 FAMILY Pin Diagrams 44-PIN TQFP, (1,3) 44-Pin QFN RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V /V CAP DDCORE PGED2/RP10/CN16/PMD2/RB10 PGEC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/C1INC/RP13/PMRD/REFO/CN13/RB13 Legend: RPn represents remappable peripheral pins. Note 1: Gray shading indicates 5.5V tolerant input pins. 2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. ...
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... Electrical Characteristics .......................................................................................................................................................... 259 29.0 Packaging Information.............................................................................................................................................................. 277 Appendix A: Revision History............................................................................................................................................................. 287 The Microchip Web Site ..................................................................................................................................................................... 295 Customer Change Notification Service .............................................................................................................................................. 295 Customer Support .............................................................................................................................................................................. 295 Reader Response .............................................................................................................................................................................. 296 Product Identification System ............................................................................................................................................................ 297 © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 5 ...
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... PIC24FJ64GA104 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ64GA104 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • ...
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... These are summarized in Table 1-1. A list of PIC24FJ64GA104 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of this data sheet ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA104 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...
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... PIC24FJ64GA104 FAMILY FIGURE 1-1: PIC24FJ64GA104 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control OSCO/CLKO OSCI/CLKI Power-up Timing Timer Generation Oscillator Start-up Timer FRC/LPRC ...
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... TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS Pin Number 28-Pin 44-Pin Function 28-Pin SPDIP/ QFN SOIC TQFP AN0 2 27 AN1 3 28 AN2 4 1 AN3 5 2 AN4 6 3 AN5 7 4 AN6 — — AN7 — — AN8 — — AN9 26 23 AN10 25 22 ...
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... PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin 44-Pin Function 28-Pin SPDIP/ QFN SOIC TQFP CN0 12 9 CN1 11 8 CN2 2 27 CN3 3 28 CN4 4 1 CN5 5 2 CN6 6 3 CN7 7 4 CN8 — — CN9 — — ...
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... TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin 44-Pin Function 28-Pin SPDIP/ QFN SOIC TQFP INT0 16 13 MCLR 1 26 OSCI 9 6 OSCO 10 7 PGEC1 5 2 PGED1 4 1 PGEC2 22 19 PGED2 21 18 PGEC3 15 12 PGED3 14 11 PMA0 10 7 PMA1 12 9 PMA2 — ...
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... PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin 44-Pin Function 28-Pin SPDIP/ QFN SOIC TQFP RA0 2 27 RA1 3 28 RA2 9 6 RA3 10 7 RA4 12 9 RA7 — — RA8 — — RA9 — — RA10 — — ...
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... TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin 44-Pin Function 28-Pin SPDIP/ QFN SOIC TQFP RP0 4 1 RP1 5 2 RP2 6 3 RP3 7 4 RP4 11 8 RP5 2 27 RP6 3 28 RP7 16 13 RP8 17 14 RP9 18 15 RP10 21 18 RP11 22 19 ...
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... PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin 44-Pin Function 28-Pin SPDIP/ QFN SOIC TQFP CAP V 13, 28 10 DDCORE REF REF 29 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39951B-page 16 Input I/O Buffer QFN — ...
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... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24FJ64GA104 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
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... PIC24FJ64GA104 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... PIC24FJ64GA104 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... PIC24FJ64GA104 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...
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... W13 W14 W15 22 PUSH.S Registers or bits shaded for © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...
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... PIC24FJ64GA104 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ64GA104 FAMILY 3.3.2 DIVIDER The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
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... Program Address Space The program address memory PIC24FJ64GA104 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA104 FAMILY DEVICES PIC24FJ32GA10X GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash ...
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... On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ64GA104 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1. ...
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... Section 4.3.3 “Reading Data from Program Memory Using Program Space Visibility”). FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA104 FAMILY DEVICES MSB Address 0001h 07FFh ...
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... PIC24FJ64GA104 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE (1) CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE (1) ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-7: INPUT CAPTURE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A ...
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TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
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TABLE 4-11: SPI REGISTER MAPS File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — SPI1BUF 0248 SPI2STAT 0260 SPIEN — ...
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TABLE 4-15: PAD CONFIGURATION REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PADCFG1 02FC — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-16: ADC REGISTER ...
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TABLE 4-18: PARALLEL MASTER/SLAVE PORT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 PMADDR 0604 — CS1 — — PMDOUT1 PMDOUT2 0606 ...
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TABLE 4-21: COMPARATORS REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMIDL — — — CVRCON 0652 — — — — CM1CON 0654 CEN COE CPOL — CM2CON 065C CEN COE CPOL — ...
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TABLE 4-23: SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — — ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... PIC24FJ64GA104 FAMILY TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) Configuration Program Space Visibility User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG< ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PIC24FJ64GA104 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i ...
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... Run-Time Self-Programming (RTSP) • JTAG • Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ64GA104 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx ...
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... PIC24FJ64GA104 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY (1) U-0 U-0 — — (1) U-0 ...
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... PIC24FJ64GA104 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is as follows: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...
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... PIC24FJ64GA104 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS (C LANGUAGE CODE example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 unsigned int offset; unsigned int i; unsigned long progAddr = 0xXXXXXX; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; //Set up NVMCON for row programming NVMCON = 0x4001; //Set up pointer to the first memory location to be written TBLPAG = progAddr> ...
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... Microchip Technology Inc. PIC24FJ64GA104 FAMILY instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to ‘ ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 54 Preliminary © 2009 Microchip Technology Inc. ...
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... Illegal Opcode Configuration Mismatch Uninitialized W Register © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
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... PIC24FJ64GA104 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Clear Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit ...
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... BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY (1) (CONTINUED) Setting Event 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the System Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... PIC24FJ64GA104 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source (6) POR EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL All Others Any Clock Note Power-on Reset delay. ...
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... FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 6.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associ- ated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 60 Preliminary © 2009 Microchip Technology Inc. ...
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... These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...
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... PIC24FJ64GA104 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — ...
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... SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah 00019Ah 77 ...
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... PIC24FJ64GA104 FAMILY 7.3 Interrupt Control and Status Registers The PIC24FJ64GA104 family of devices implements the following registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS4 • IEC0 through IEC4 • IPC0 through IPC20 (except IPC13, IPC14 and IPC17) • ...
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... See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 — — ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 — — CTMUIF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 — IC1IP2 IC1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP< ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 — SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP< ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 — MI2C1IP2 MI2C1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP< ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 86
... PIC24FJ64GA104 FAMILY REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP2 T4IP1 bit 15 U-0 R/W-1 R/W-0 — OC3IP2 OC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP< ...
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... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — ...
Page 88
... PIC24FJ64GA104 FAMILY REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SPI2IP2 SPI2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP< ...
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... IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — ...
Page 90
... PIC24FJ64GA104 FAMILY REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — OC5IP2 OC5IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP< ...
Page 91
... PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 U-0 PMPIP0 — ...
Page 92
... PIC24FJ64GA104 FAMILY REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SI2C2IP2 SI2C2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP< ...
Page 93
... RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — ...
Page 94
... PIC24FJ64GA104 FAMILY REGISTER 7-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 — CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 — U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP< ...
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... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
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... PIC24FJ64GA104 FAMILY REGISTER 7-32: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 CPUIRQ — VHOLD bit 15 U-0 R-0 R-0 — VECNUM6 VECNUM5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit interrupt request has occurred but has not yet been Acknowledged by the CPU ...
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... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 98
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 96 Preliminary © 2009 Microchip Technology Inc. ...
Page 99
... For more information, refer to the “PIC24F Family Reference “Section 6. Oscillator” (DS39700). The oscillator system for PIC24FJ64GA104 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • On-chip 4x PLL to boost internal operating frequency ...
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... PIC24FJ64GA104 FAMILY 8.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal 4x PLL ...
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... IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator. ...
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... PIC24FJ64GA104 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...
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... MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...
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... PIC24FJ64GA104 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
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... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. ...
Page 106
... Secondary Oscillator (SOSC) 8.5.1 BASIC SOSC OPERATION PIC24FJ64GA104 family devices do not have to set the SOSCEN bit to use the Secondary Oscillator. Any module requiring the SOSC (such as RTCC, Timer1 or DSWDT) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long start-up time ...
Page 107
... Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 ...
Page 108
... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 106 Preliminary © 2009 Microchip Technology Inc. ...
Page 109
... Family Reference Section 39. “Power-Saving Features with Deep Sleep” (DS39727). The PIC24FJ64GA104 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...
Page 110
... Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 9.2.4 DEEP SLEEP MODE In PIC24FJ64GA104 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available, without requiring the use of external switches to completely remove all power from the device ...
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... PWRSAV instruction, in the event that the PWRSAV instruction is skipped and the device does not enter Deep Sleep mode. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Examples for implementing these cases are shown in Example 9- recommended that an assembler, or in-line C routine be used in these cases, to ensure that the code executes in the number of cycles required ...
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... PIC24FJ64GA104 FAMILY 9.2.4.3 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • POR event on V supply. If there is no DSBOR DD circuit to re-arm the V supply POR circuit, the DD external V supply must be lowered to the DD natural arming voltage of the POR circuit. ...
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... CW4 Configuration register and DSWDT configuration options, refer to Section 25.0 “Special Features”. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.2.4.8 Switching Clocks in Deep Sleep Mode Both the RTCC and the DSWDT may run from either SOSC or the LPRC clock source. This allows both the ...
Page 114
... PIC24FJ64GA104 FAMILY 9.2.4.10 Power-on Resets ( PORs V voltage is monitored to produce PORs. Since exit- DD ing from Deep Sleep functionally looks like a POR, the technique described in Section 9.2.4.9 “Checking and Clearing the Status of Deep Sleep” should be used to distinguish between Deep Sleep and a true POR event ...
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... Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR. 3: This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — ...
Page 116
... PIC24FJ64GA104 FAMILY REGISTER 9-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0, HS U-0 U-0 (1) DSFLT — — bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
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... CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 116 Preliminary © 2009 Microchip Technology Inc. ...
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... Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
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... PIC24FJ64GA104 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits con- figures the corresponding pin to act as an open-drain output ...
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... Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ64GA104 family of devices to gen- erate interrupt requests to the processor in response to a Change-Of-State (COF) on selected input pins. This feature is capable of detecting input Change-Of-States even in Sleep mode, when the clocks are disabled. ...
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... PIC24FJ64GA104 FAMILY 10.4.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint ...
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... IrDA BCLK functionality uses this output. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-3). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘000000’. ...
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... PIC24FJ64GA104 FAMILY 10.4.3.3 Mapping Limitations The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input, or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility ...
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... To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled were tied to a fixed pin ...
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... PIC24FJ64GA104 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS The PIC24FJ64GA104 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — ...
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... T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-1 R/W-1 R/W-1 T3CKR4 T3CKR3 ...
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... PIC24FJ64GA104 FAMILY REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
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... OCFBR<4:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ64GA104 FAMILY REGISTER 10-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 131
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-1 R/W-1 R/W-1 SCK1R4 SCK1R3 SCK1R2 R/W-1 ...
Page 132
... PIC24FJ64GA104 FAMILY REGISTER 10-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP2 (see Table 10-3 for peripheral function numbers). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 RP1R4 RP1R3 RP1R2 ...
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... PIC24FJ64GA104 FAMILY REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: RP10 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP10 (see Table 10-3 for peripheral function numbers). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 RP9R4 RP9R3 RP9R2 ...
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... PIC24FJ64GA104 FAMILY REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
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... RP18R<4:0>: RP18 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP18 (see Table 10-3 for peripheral function numbers). Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 RP17R4 ...
Page 138
... PIC24FJ64GA104 FAMILY REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 139
... RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table 10-3 for peripheral function numbers). Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 RP25R4 ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 138 Preliminary © 2009 Microchip Technology Inc. ...
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... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
Page 142
... PIC24FJ64GA104 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 143
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). 2. ...
Page 144
... PIC24FJ64GA104 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal MSB Reset (1) Read TMR2 (TMR4) (1) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...
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... The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information. 2: The ADC event trigger is available only on Timer3. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 1x Gate Sync 01 00 ...
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... PIC24FJ64GA104 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When TxCON<3> ...
Page 147
... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 (1) — — ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 146 Preliminary © 2009 Microchip Technology Inc. ...
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... Section 34. “Input Capture Dedicated Timer” (DS39722). Devices in the PIC24FJ64GA104 family all feature 9 independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: • ...
Page 150
... PIC24FJ64GA104 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The ...
Page 151
... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 ICTSEL2 ICTSEL1 ICTSEL0 ...
Page 152
... PIC24FJ64GA104 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0, HS U-0 ICTRIG TRIGSTAT — bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
Page 153
... Family Reference Section 35. “Output Capture with Dedicated Timer” (DS39723). Devices in the PIC24FJ64GA104 family all feature 9 independent output compare modules. Each of these modules offers a wide range of configuration and oper- ating options for generating pulse trains on internal device events, and can produce Pulse-Width Modulated (PWM) waveforms for driving power applications ...
Page 154
... PIC24FJ64GA104 FAMILY FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Increment Clock OC Clock Select Sources Match Event Trigger and Trigger and Sync Sources Sync Logic Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” ...
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... Trigger mode operation starts after a trigger source event occurs. 8. Set the OCM<2:0> bits for the appropriate compare operation (= 0xx). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. Set the OC32 (OCyCON2< ...
Page 156
... PIC24FJ64GA104 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare module for PWM operation: 1 ...
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... T , Doze mode and PLL are disabled. CY OSC © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 14.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i ...
Page 158
... PIC24FJ64GA104 FAMILY 14.4 Subcycle Resolution The DCB bits (OCxCON2<10:9>) provide for resolution better than one instruction cycle. When used, they delay the falling edge generated by a match event by a portion of an instruction cycle. For example, setting DCB<1:0> causes the falling edge to occur halfway through the instruction cycle in which the match event occurs, instead of at the beginning ...
Page 159
... Pin Select (PPS)”. 2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 R/W-0 R/W-0 OCTSEL2 ...
Page 160
... PIC24FJ64GA104 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 2-0 OCM<2:0>: Output Compare x Mode Select bits 111 = Center-Aligned PWM mode on OCx 110 = Edge-Aligned PWM mode on OCx 101 = Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously ...
Page 161
... SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCM bits (OCxCON1<1:0>) = 001. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY R/W-0 U-0 R/W-0 (3) OCINV DCB1 — ...
Page 162
... PIC24FJ64GA104 FAMILY REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module 11110 = Reserved 11101 = Reserved (2) 11100 = CTMU (2) 11011 = A/D 11010 = Comparator 3 11001 = Comparator 2 11000 = Comparator 1 10111 = Input Capture 4 10110 = Input Capture 3 10101 = Input Capture 2 ...
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... EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI ® module is compatible with Motorola interfaces. All devices of the PIC24FJ64GA104 family include three SPI modules The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer ...
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... PIC24FJ64GA104 FAMILY To set up the SPI module for the Standard Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. ...
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... SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...
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... PIC24FJ64GA104 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 (1) SPIEN — SPISIDL bit 15 R-0 R/C-0, HS R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
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... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 165 ...
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... PIC24FJ64GA104 FAMILY REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (4) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
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... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer enabled 0 = Enhanced buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — — ...
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... PIC24FJ64GA104 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (2) (SPIxBUF) MSTEN (SPIxCON1<5> Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...
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... FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx ...
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... PIC24FJ64GA104 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 15-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2, Doze mode and PLL are disabled. CY OSC 2: SCKx frequencies shown in kHz. DS39951B-page 170 ...
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... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 16-1. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 16.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
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... PIC24FJ64GA104 FAMILY 2 FIGURE 16-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39951B-page 172 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
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... The address will be Acknowledged only if GCEN = match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 16.3 Slave Address Masking The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
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... PIC24FJ64GA104 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module ...
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... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2 C master. Applicable during master receive master ...
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... PIC24FJ64GA104 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC IWCOL I2COV D/A bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ...
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... TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 2 C slave device address byte. Preliminary DS39951B-page 177 ...
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... PIC24FJ64GA104 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
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... The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...
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... PIC24FJ64GA104 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: ...
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... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 17.2 “Transmitting in 8-Bit Data Mode”). ...
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... PIC24FJ64GA104 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled ...
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... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 183 ...
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... PIC24FJ64GA104 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
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... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 185 ...
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... PIC24FJ64GA104 FAMILY NOTES: DS39951B-page 186 Preliminary © 2009 Microchip Technology Inc. ...
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... Parallel Master Port (1) Note 1: PMA<10:2> bits are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Key features of the PMP module include: • Programmable Address Lines • One Chip Select Line • Programmable Strobe Options: - Individual Read and Write Strobes or; ...
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... PIC24FJ64GA104 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 PMPEN — PSIDL bit 15 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PMPEN: Parallel Master Port Enable bit ...
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... For Master Mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: PMA<10:2> bits are not available on 28-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Preliminary DS39951B-page 189 ...
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... PIC24FJ64GA104 FAMILY REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 15 R/W-0 R/W-0 R/W-0 (1) (1) WAITB1 WAITB0 WAITM3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 BUSY: Busy bit (Master mode only) ...
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... PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads function as port I/O Note 1: PMA<10:2> bits are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 — — ADDR10 ...
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... PIC24FJ64GA104 FAMILY REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 IBF IBOV — bit 15 R-1 R/W-0, HS U-0 OBE OBUF — bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IBF: Input Buffer Full Status bit ...
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... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set. © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ64GA104 FAMILY FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS1 PMRD PMWR FIGURE 18-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PMA<1:0> PMD<7:0> PMCS1 PMRD PMWR Address Bus Data Bus Control Lines TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION PMA<1:0> Output Register (Buffer) 00 PMDOUT1< ...
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... PMALL PMALH PMCS1 PMRD PMWR FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 PMALL PMRD PMWR PMD<7:0> PMA<7:0> PMA<15:8> PMCS1 PMALL PMALH PMRD PMWR A< ...
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... PIC24FJ64GA104 FAMILY FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA) PIC24F PMA<n:0> PMD<7:0> PMCS1 PMRD PMWR FIGURE 18-11: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA) PIC24F PMA< ...
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... Comparator Alarm Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC24FJ64GA104 FAMILY • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • ...
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... PIC24FJ64GA104 FAMILY 19.2 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.2.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers ...