DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 26

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.0
11.1
ICSP mode is a special programming protocol that
allows you to read and write to dsPIC30F SMPS
programming executive. The ICSP mode is the second
(and slower) method used to program the device. This
mode also has the ability to read the contents of exec-
utive memory to determine if the programming execu-
tive is present. This capability is accomplished by
applying control codes and instructions serially to the
device using pins PGC and PGD.
In ICSP mode, the system clock is taken from the PGC
pin, regardless of the device’s oscillator Configuration
bits. All instructions are first shifted serially into an
internal buffer, then loaded into the instruction register
and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGD is used to shift data in, and PGC is used as
both the serial shift clock and the CPU execution clock.
Data is transmitted on the rising edge and latched on
the falling edge of PGC. For all data transmissions, the
Least Significant bit (LSb) is transmitted first.
11.2
Upon entry into ICSP mode, the CPU is idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGC and PGD,
and this control code is used to command the CPU
(see
The SIX control code is used to send instructions to the
CPU for execution, while the REGOUT control code is
used to read data out of the device via the VISI register.
The operation details of ICSP mode are provided in
Section 11.2.1 “Six Serial Instruction Execution”
and
Execution”.
DS70284C-page 26
Note 1: During ICSP operation, the operating
Table
Section 11.2.2 “REGOUT Serial Instruction
2: On the first serial word (in ICSP mode) to
3: Because ICSP is slower, it is recom-
ICSP™ MODE
ICSP Mode
ICSP Operation
11-1).
frequency of PGC must not exceed
5 MHz.
be shifted into the device following a
Reset, an additional 5 clocks must be
provided to the device on the PGC pin.
mended that only Enhanced ICSP mode
be used for device programming, as
described in
the Programming
Section 5.1 “Overview of
Process”.
TABLE 11-1:
11.2.1
The SIX control code allows execution of dsPIC30F
SMPS assembly instructions. When the SIX code is
received, the CPU is suspended for 24 clock cycles as
the instruction is then clocked into the internal buffer.
Once the instruction is shifted in, the state machine
allows it to be executed over the next four clock cycles.
While the received instruction is executed, the state
machine simultaneously shifts in the next 4-bit
command (see
11.2.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGD pin. Once the REGOUT control code is
received, eight clock cycles are required to process the
command. During this time, the CPU is held idle. After
these eight cycles, an additional 16 cycles are required
to clock the data out (see
The REGOUT instruction is unique because the PGD
pin is an input when the control code is transmitted to
the device. However, once the control code is
processed, the PGD pin becomes an output as the VISI
register is shifted out. After the contents of the VISI are
shifted out, PGD becomes an input again as the state
machine holds the CPU idle until the next 4-bit control
code is shifted in.
Control Code
0000b
0001b
0010b-1111b
Note:
Note 1: Coming out of Reset, the first 4-bit control
4-bit
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
SIX SERIAL INSTRUCTION
EXECUTION
REGOUT SERIAL INSTRUCTION
EXECUTION
Once the contents of VISI are shifted out,
the dsPIC
as an output until the first rising edge of
the next clock is received.
code is always forced to SIX, and a forced
NOP instruction is executed by the CPU.
Once the forced SIX is clocked in, ICSP
operation resumes as normal (the next 24
clock cycles load the first instruction word
to the CPU).
instructions must be followed by a NOP
instruction.
Figure
Mnemonic
SIX
REGOUT
N/A
CPU CONTROL CODES IN
ICSP™ MODE
®
11-2).
© 2010 Microchip Technology Inc.
DSC device maintains PGD
Figure
Shift in 24-bit
instruction and execute.
Shift out the VISI
register.
Reserved.
11-3).
Description