DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 14

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
32. Module: UART
33. Module: UART
34. Module: UART
DS80445D-page 14
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Affected Silicon Revisions
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
• The UART receive interrupt is set to occur
• More than two bytes with an error are received
In these two circumstances, only the first two bytes
with a parity or framing error will have the
corresponding bits indicate correctly. The error bits
will not be set after this.
Work around
None.
Affected Silicon Revisions
A1
A1
A1
X
X
when the FIFO is full or three-quarters full
(U1STA<7:6> = 1x), and
X
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
35. Module: I
36. Module: I
37. Module: I
The Bus Collision Status bit (BCL) is not set when
a bus collision occurs during a Restart or Stop
event. However, the BCL bit is set when a bus
collision occurs during a Start event.
Work around
None.
Affected Silicon Revisions
Writing to I2CxTRN during a Start bit transmission
generates a write collision, indicated by the
IWCOL bit (I2CxSTAT<7>) being set. In this state,
additional writes to the I2CxTRN register should
be blocked. However, in this condition, the
I2CxTRN register can be written, although
transmissions will not occur until the IWCOL bit is
cleared in software.
Work around
After each write to the I2CxTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software, and I2CxTRN must be rewritten.
Affected Silicon Revisions
The ACKSTAT bit (I2CxSTAT<15>) reflects the
received
transmissions, but not for slave transmissions. As
a result, a slave cannot use this bit to determine
whether it received an ACK or a NACK from a
master. In future silicon revisions, the ACKSTAT
bit will reflect received ACK/NACK status for both
master and slave transmissions.
Work around
After transmitting a byte, the slave should poll the
SDA line (subject to a time-out period that is
dependent on the application) to determine
whether an ACK (‘0’) or a NACK (‘1’) was
received.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
A2
X
X
X
2
2
2
ACK/NACK
C
C
C
A3
A3
A3
X
X
X
© 2010 Microchip Technology Inc.
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