DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
11. PWM Override Enable
12. EXTREF Pin
13. Output Compare Module
14. Output Compare Module in PWM Mode
15. SPI Module in Frame Master Mode
16. SPI Module in Slave Select Mode
17. SPI Module
18. I
19. MCLR pin
20. UART Module
21. UART Module
22. UART Module
23. UART Module
DS80290J-page 2
The PWM override feature does not work correctly.
The EXTREF pin is susceptible to voltage spikes
below V
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
The output compare module will miss one
compare event when the duty cycle register value
is updated from 0x0000 to 0x0001.
The SPI module will fail to generate frame
synchronization pulses in Frame Master mode if
FRMDLY = 1.
The SPI module Slave Select functionality will not
work correctly.
The SMP bit does not have any effect when the
SPI module is configured for a 1:1 prescale factor
in Master mode.
The bus collision status bit does not get set when
a bus collision occurs during a Restart or Stop
event.
When the dsPIC
enabled, the MCLR pin does not operate correctly
in the event of a brown-out condition.
If the Baud Rate Generator register (BRG)
contains an odd value and the parity option is
enabled, the module may falsely indicate parity
errors.
The Receive Buffer Overrun Error Status bit may
be set prematurely.
UART receptions may be corrupted in high baud
rate mode (BRGH = 1).
UTXISEL0 bit in the UxSTA register is always read
as zero regardless of the value written to it.
2
C™ Module
SS
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DSC is operated with the PLL
24. UART Module
25. UART Module
26. I
27. I
28. I
29. UART Module (IrDA
30. UART Module
31. Output Compare Module
32. PWM Duty Cycle
33. PWM Jitter
34. PWM Override Priority
35. Decimal Adjust Instruction
36. Sleep Mode
The auto-baud feature does not work properly in
high baud rate mode (BRGH = 1).
When the auto-baud feature is enabled, the sync
break character (0x55) may be loaded into the
FIFO as data.
The I2CxTRN register can be written to even if a
write collision is detected.
The ACKSTAT bit does not reflect the status of a
transmission received from an I
The D_A Status bit in the I2CxSTAT register does
not get set on a write to the I2CxTRN register by
an I
The operation of the RXINV bit in the UxMODE
register is inverted.
The auto-baud feature measures baud rate
inaccurately for certain baud rate and clock speed
combinations.
In Dual Compare Match mode, the OCx output is
not reset when the OCxR and OCxRS registers
are loaded with values having a difference of ‘1’.
When the PWM module is operated with
Immediate Duty Cycle updates enabled, any duty
cycle value less than or equal to 0x0010 causes
the PWM outputs to flip to the inverted state.
The PWM output may exhibit an occasional jitter
proportional to the operating speed of the
dsPIC30F1010/202X device.
The PWM Fault, Current-Limit and Output
Override priorities do not work correctly.
The decimal adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>).
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
2
2
2
C Module
C Module
C Module
2
C Slave device.
© 2008 Microchip Technology Inc.
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Reception)
2
C Slave device.