DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 12

IC DSPIC MCU/DSP 6K 28SOIC

DSPIC30F1010-30I/SO

Manufacturer Part Number
DSPIC30F1010-30I/SO
Description
IC DSPIC MCU/DSP 6K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F1010-30I/SO
Manufacturer:
Microchip Technology
Quantity:
135
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DSPIC30F1010-30I/SO
Manufacturer:
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Quantity:
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dsPIC30F1010/202X
20. Module: UART Module
21. Module: UART Module
22. Module: UART Module
DS80290J-page 12
With the parity option enabled, a parity error,
indicated by the PERR bit (UxSTA<3>) being set,
may occur if the Baud Rate Generator contains an
odd value. This affects both even and odd parity
options.
Work around
Load the Baud Rate Generator register, UxBRG,
with an even value, or disable the peripheral’s
parity option by loading either 0b00 or 0b11 into
the Parity and Data Selection bits, PDSEL<1:0>
(UxMODE<2:1>).
The Receive Buffer Overrun Error Status bit,
OERR (UxSTA<1>), may set before the UART
FIFO has overflowed. After the fourth byte is
received by the UART, the FIFO is full. The OERR
bit should set after the fifth byte has been received
in the UART shift register. Instead, the OERR bit
may set after the fourth received byte with the
UART Shift register empty.
Work around
After four bytes have been received by the UART,
the UART Receiver Interrupt Flag bit, U1RXIF
(IFS0<11>), will be set, indicating the UART FIFO
is full. The OERR bit may also be set. After reading
the UART receive buffer, UxRXREG, four times to
clear the FIFO, clear both the OERR and UxRXIF
bits in software.
UART receptions may be corrupted if the Baud
Rate Generator (BRGH) is set up for 4x mode
(BRGH = 1).
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
23. Module: UART Module
24. Module: UART Module
25. Module: UART Module
The UTXISEL0 bit (UxSTA<13>) is always read as
zero regardless of the value written to it. The bit
can be written to either a ‘0’ or ‘1’, but will always
be read as zero. This will affect read-modify-write
operations such as bitwise or shift operations.
Using a read-modify-write instruction on the
UxSTA register (e.g., BSET, BLCR) will always
write the UTXISEL0 bit to zero.
Work around
If a UTXISEL0 value of ‘1’ is needed, avoid using
read-modify-write instructions on the UxSTA
register.
Copy the UxSTA register to a temporary variable
and
read-modify-write operations. Copy the new value
back to the UxSTA register.
The auto-baud feature may not calculate the
correct baud rate when the High Baud Rate
Enable bit, BRGH, is set. With the BRGH set, the
baud rate calculation used is the same as
BRG = 0.
Work around
If the auto-baud feature is needed, use the Low
Baud Rate mode by clearing the BRGH bit.
With the auto-baud feature selected, the sync
break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the sync break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
set
UxSTA<13>
© 2008 Microchip Technology Inc.
prior
to
performing

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