PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 144
PIC18F27J53-I/SP
Manufacturer Part Number
PIC18F27J53-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/SP
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F27J53-I/SP
Manufacturer:
MITSUBISHI
Quantity:
12
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 144 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
REGISTER 10-2:
REGISTER 10-3:
DS39964B-page 144
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
CCP10OD: CCP10 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
CCP9OD: CCP9 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U2OD: USART2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U1OD: USART1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
Unimplemented: Read as ‘0’
SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U-0
U-0
—
—
ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h)
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP10OD
R/W-0
U-0
—
CCP9OD
R/W-0
U-0
—
2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
SPI2OD
R/W-0
U2OD
R/W-0
SPI1OD
R/W-0
U1OD
R/W-0
bit 0
bit 0
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