PIC24HJ16GP304-I/ML Microchip Technology, PIC24HJ16GP304-I/ML Datasheet - Page 97

• Manufacturer Part Number: PIC24HJ16GP304-I/ML
• Description: IC PIC MCU FLASH 16K 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ16GP304-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4
A major challenge in general purpose devices is
providing the largest possible set of peripheral features
while minimizing the conflict of features on I/O pins.
The challenge is even greater on low-pin count
devices. In an application where more than one
peripheral must be assigned to a single pin, inconve-
nient workarounds in application code or a complete
redesign may be the only option.
Peripheral pin select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The peripheral pin select configuration feature
operates over a fixed subset of digital I/O pins. Pro-
grammers can independently map the input and/or out-
put of most digital peripherals to any one of these I/O
pins. Peripheral pin select is performed in software,
and generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
9.4.1
The peripheral pin select feature is used with a range
of up to 26 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
9.4.2
only peripherals. These include:
• General serial communications (UART and SPI)
• General-purpose timer clock inputs
• Timer-related peripherals (input capture and out-
• Interrupt-on-change inputs.
In comparison, some digital-only peripheral modules
are never included in the peripheral pin select feature.
This is because the peripheral’s function requires spe-
cial I/O circuitry on a specific port and cannot be easily
connected to multiple pins. These modules include I
A similar requirement excludes all modules with analog
inputs, such as the Analog-to-Digital Converter (ADC).
© 2007 Microchip Technology Inc.
The peripheral pin select feature manages all digital-
put compare)
Peripheral Pin Select
AVAILABLE PINS
AVAILABLE PERIPHERALS
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
2
C.
Remappable peripherals are not associated with a
default I/O pin. The peripheral must always be
assigned to a specific I/O pin before it can be used. In
contrast, non remappable peripherals are always avail-
able on a default pin, assuming that the peripheral is
active and not conflicting with another peripheral.
9.4.2.1
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
9.4.3
Peripheral pin select features are controlled through
two sets of special function registers to map peripher-
als and to map outputs.
Since they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
9.4.3.1
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral. A control regis-
ter associated with a peripheral dictates the pin it will be
mapped to. The RPINRx registers are used to config-
ure peripheral input mapping (see Register 9-1 through
Register 9-9). Each register contains sets of 5-bit
fields, with each set associated with one of the remap-
pable peripherals. Programming a given peripheral’s
bit field with an appropriate 5-bit value maps the RPn
pin with that value to that peripheral. For any given
device, the valid range of values for any bit field corre-
sponds to the maximum number of peripheral pin
selections supported by the device.
Figure 9-2 Illustrates remappable pin selection for
U1RX input.
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select Function
Priority
Input Mapping
DS70289A-page 95