PIC24HJ16GP304-I/ML Microchip Technology, PIC24HJ16GP304-I/ML Datasheet
PIC24HJ16GP304-I/ML
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PIC24HJ16GP304-I/ML Summary of contents
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... PIC24HJ32GP202/204 and © 2007 Microchip Technology Inc. PIC24HJ16GP304 Data Sheet High-Performance, 16-bit Microcontrollers Preliminary DS70289A ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash program memory ( Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash © 2007 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Communication Modules: • 4-wire SPI - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes 2 • I C™ - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 PIC24HJ32GP202/204 and PIC24HJ16GP304 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONTROLLER FAMILIES Device PIC24HJ32GP202 28 32 PIC24HJ32GP204 44 32 PIC24HJ16GP304 44 16 Note 1: Only 2 out of 3 timers are Remappable © ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Pin Diagrams 28-Pin SDIP, SOIC AN0/V REF AN1/V REF PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/RP4/CN1/RB4 SOSCO/T1CK/CN0/RA4 PGED3/ASDA1/RP5/CN27/RB5 28-Pin QFN-S PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 DS70289A-page 4 MCLR +/CN2/RA0 -/CN3/RA1 AN9/RP15/CN11/RB15 3 26 AN10/RP14/CN12/RB14 4 25 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4 © 2007 Microchip Technology Inc. 11 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 25 9 PGEC2/RP11/CN15/RB11 8 26 PGED2/RP10/CN16/RB10 CAP PIC24HJ32GP204 PIC24HJ16GP304 5 29 RP25/CN19/RC9 4 RP24/CN20/RC8 RP23/CN17/RC7 2 32 RP22/CN18/RC6 1 33 SDA1/RP9/CN21/RB9 Preliminary /V DDCORE ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4 DS70289A-page 6 11 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 25 9 PGEC2/RP11/CN15/RB11 8 26 PGED2/RP10/CN16/RB10 CAP PIC24HJ32GP204 PIC24HJ16GP304 5 29 RP25/CN19/RC9 4 30 RP24/CN20/RC8 3 RP23/CN17/RC7 RP22/CN18/RC6 1 SDA1/RP9/CN21/RB9 33 Preliminary /V DDCORE © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU............................................................................................................................................................................................ 13 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Flash Program Memory.............................................................................................................................................................. 41 5.0 Resets ....................................................................................................................................................................................... 47 6.0 Interrupt Controller ..................................................................................................................................................................... 53 7.0 Oscillator Configuration .............................................................................................................................................................. 81 8.0 Power-Saving Features.............................................................................................................................................................. 91 9.0 I/O Ports ..................................................................................................................................................................................... 93 10.0 Timer1 ...................................................................................................................................................................................... 117 11.0 Timer2/3 Feature...................................................................................................................................................................... 119 12.0 Input Capture............................................................................................................................................................................ 125 13 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 8 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202 • PIC24HJ32GP204 • PIC24HJ16GP304 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007 Microchip Technology Inc. and ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 1-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCU PCH PCL 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Name Pin Type Buffer Type AN0-AN12 I Analog CLKI I ST/CMOS CLKO O — OSC1 I ST/CMOS OSC2 I/O — SOSCI I ST/CMOS SOSCO O — CN0-CN30 I ST IC1-IC2 I ST IC7-IC8 OCFA I ST OC1-OC2 O — INT0 I ST INT1 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Type Buffer Type VDD MCLR I VSS V P — DD Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels DS70289A-page 12 Description Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. ...
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... operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the PIC24HJ32GP202/ 204 and PIC24HJ16GP304 is shown in Figure 2-2. © 2007 Microchip Technology Inc. 2.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU) ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 2-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 2-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2007 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 2.3 CPU Control Registers REGISTER 2-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (2) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 2-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ ...
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... Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for more information on the SR bits affected by each instruction. The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU incorporates hardware support for both multiplica- tion and division. This includes a dedicated hardware multiplier and a support hardware for 16-bit divisor divi- sion ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices are shown in Figure 3-1. 0x000000 0x000002 0x000004 Interrupt Vector Table ...
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... Byte (read as ‘0’) DS70289A-page 20 3.1.2 INTERRUPT AND TRAP VECTORS All PIC24HJ32GP202/204 and PIC24HJ16GP304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code ...
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... DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24HJ32GP202/204 and PIC24HJ16GP304 instruc- tion set supports both word and byte operations consequence of byte accessibility, all effective address calculations are internally scaled to step through word- aligned memory ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 3-3: DATA MEMORY MAP FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES WITH 2 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 2 Kbyte SRAM Space 0x0FFF 0x1001 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70289A-page 22 LSB 16 bits ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 23 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 24 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 25 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 26 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 27 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 28 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 29 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 30 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 31 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 33 ...
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... In addition to its use as a working register, the W15 register in the PIC24HJ32GP202/204 PIC24HJ16GP304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post- increments for stack pushes, as shown in Figure 3-4. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 3.3.3 MOVE (MOV) INSTRUCTION Move instructions provide a greater degree of address- ing flexibility than the other instructions ...
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... To use this data successfully, it must be accessed in a way that pre- serves the alignment of information in both spaces. Aside from normal execution, the PIC24HJ32GP202/ 204 and PIC24HJ16GP304 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method to read or write the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only methods to read or write the upper 8 bits of a pro- gram space word as data ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to the stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 40 Preliminary © 2007 Microchip Technology Inc. ...
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... Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ32GP202/204 PIC24HJ16GP304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/ PGD1, PGC2/PGD2 or PGC3/PGD3), and three other ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 4.2 RTSP Operation The PIC24HJ32GP202/204 and PIC24HJ16GP304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to pro- gram one row or one word at a time. The 8-row erase ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE — bit 7 Legend Satiable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 4-2: NVMKEY: NON-VOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Satiable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY Programmers can program one row of program Flash memory at a time this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...
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... RESETS Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 5-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-up Reset has occurred Power-up Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 5.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 7.0 “Oscillator Configuration” for further details ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 5.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released. • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 52 Preliminary © 2007 Microchip Technology Inc. ...
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... INTERRUPT CONTROLLER Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The PIC24HJ32GP202/204 and PIC24HJ16GP304 interrupt controllers reduce the numerous peripheral ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 6-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 6-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address Number Number 8 0 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 6-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 6.3 Interrupt Control and Status Registers PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement a total of 17 registers for the inter- rupt controller: • Interrupt Control Register 1 (INTCON1) • Interrupt Control Register 2 (INTCON2) • Interrupt Flag Status Registers (IFSx) • Interrupt Enable Control Registers (IECx) • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 3 IPL3: CPU Interrupt Priority Level Status bit 3 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 R/W-0 U-0 — DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-7: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-10: IEC4: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-12: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-14: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP< ...
Page 76
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 77
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-16: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP< ...
Page 78
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP< ...
Page 79
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-18: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP< ...
Page 80
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 6-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ...
Page 81
... PIC24HJ32GP202/204 and PIC24HJ16GP304 6.4 Interrupt Setup Procedures 6.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 82
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 80 Preliminary © 2007 Microchip Technology Inc. ...
Page 83
... The PIC24HJ32GP202/204 and PIC24HJ16GP304 oscillator system provides: • External and internal oscillator options as clock sources • An on-chip PLL to scale the internal operating frequency to the required system clock frequency FIGURE 7-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSCO S3 OSCI S1 FRC Oscillator TUN< ...
Page 84
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F defines the operating speed of the device, and speeds MHz are supported by the PIC24HJ32GP202/ 204 and PIC24HJ16GP304 architecture. Instruction execution speed or device operating frequency given by: CY ...
Page 85
... PLL” being the selected oscillator mode. • If PLLPRE<4:0> then This yields a VCO input of 10 MHz, which is within the acceptable range of 0.8-8 MHz. FIGURE 7-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PLL BLOCK DIAGRAM Source (Crystal, External Clock PLLPRE or Internal RC) TABLE 7-1: ...
Page 86
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 87
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. ...
Page 88
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 7-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 89
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 7-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) ...
Page 90
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 7-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 91
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24HJ32GP202/204 and PIC24HJ16GP304 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD< ...
Page 92
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS-70289A-page 90 Preliminary © 2007 Microchip Technology Inc. ...
Page 93
... CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked con- stitutes lower consumed power. PIC24HJ32GP202/ 204 and PIC24HJ16GP304 devices can manage power consumption in four different ways: • Clock frequency • Instruction-based Sleep and Idle modes • ...
Page 94
... PIC24HJ32GP202/204 and PIC24HJ16GP304 8.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 95
... PIC24HJ32GP202/204 and PIC24HJ16GP304 9.0 I/O PORTS Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. All of the device pins (except OSC1/CLKI) are shared among the peripherals and the parallel I/O ports ...
Page 96
... Input Change Notification The input change notification function of the I/O ports allows the PIC24HJ16GP304 devices to generate interrupt requests to the processor in response to a change-of- state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device pin ...
Page 97
... PIC24HJ32GP202/204 and PIC24HJ16GP304 9.4 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low-pin count devices application where more than one peripheral must be assigned to a single pin, inconve- nient workarounds in application code or a complete redesign may be the only option ...
Page 98
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 9-2: REMAPPABLE MUX INPUT FOR U1RX RP0 RP1 RP2 RP 25 TABLE 9-1: REMAPPABLE PERIPHERAL INPUTS Input Name External Interrupt 1 External Interrupt 2 Timer 2 External Clock Timer 3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A ...
Page 99
... PIC24HJ32GP202/204 and PIC24HJ16GP304 9.4.3.2 Output Mapping In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. ...
Page 100
... PIC24HJ32GP202/204 and PIC24HJ16GP304 9.4.3.3 Mapping The control schema of peripheral select pins is not lim- ited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced lockouts between any of the peripheral mapping SFRs. Literally any combination of peripheral mappings across any or all of the RPn pins is possible. This includes both many-to-one and one-to-many mappings of peripheral inputs and outputs to pins ...
Page 101
... Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. 9.5 Peripheral Pin Select Registers The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement 17 registers for remappable periph- eral configuration: • Input Remappable Peripheral Registers (9) • Output Remappable Peripheral Registers (8) ...
Page 102
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 103
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 104
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 105
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 106
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-5: RPIR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 107
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 108
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 109
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-8: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 110
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 111
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-10: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 112
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-12: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTERS 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 113
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-14: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 114
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-16: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTERS 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 115
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-18: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 116
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-20: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 117
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 9-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 118
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 116 Preliminary © 2007 Microchip Technology Inc. ...
Page 119
... TIMER1 Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The Timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter ...
Page 120
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 ...
Page 121
... TIMER2/3 FEATURE Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The Timer2/3 feature has 32-bit timers that can also be configured as two independent 16-bit timers with selectable operating modes ...
Page 122
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 11-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 123
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70289A-page 121 ...
Page 124
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 11-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2/3 ...
Page 125
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 11-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 (1) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (1) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (1) bit 15 TON: Timer3 On bit 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘ ...
Page 126
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... INPUT CAPTURE Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The input capture module is useful in applications requiring frequency (period) and pulse measurement. ...
Page 128
... PIC24HJ32GP202/204 and PIC24HJ16GP304 12.1 Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 129
... PIC24HJ32GP202/204 and PIC24HJ16GP304 13.0 OUTPUT COMPARE Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. 13.1 Setup for Single Output Pulse Generation When the OCM control bits (OCxCON< ...
Page 130
... PIC24HJ32GP202/204 and PIC24HJ16GP304 13.3 Pulse-Width Modulation Mode Use the following steps when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected Timer Period register (PRy). 2. Set the PWM duty cycle by writing to the OCxRS register. 3. Write the OxCR register with the initial duty cycle. ...
Page 131
... PIC24HJ32GP202/204 and PIC24HJ16GP304 EXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS 1. Find the Timer Period register value for a desired PWM frequency that is 52.08 kHz, where F prescaler setting PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 ms PWM Period = (PR2 + 1) • 19 (PR2 + 1) • 62.5 ns • 1 ...
Page 132
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 13-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OCxRS (1) OCxR Comparator OCTSEL TMR register inputs (3) from time bases Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: OCFA pin controls OC1-OC2 channels. ...
Page 133
... PIC24HJ32GP202/204 and PIC24HJ16GP304 13.4 Output Compare Register REGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 134
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 132 Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... INTERFACE (SPI) Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices ...
Page 136
... PIC24HJ32GP202/204 and PIC24HJ16GP304 The SPI module generates an interrupt indicating com- pletion of a byte or word transfer, as well as a separate interrupt for all SPI error conditions. FIGURE 14-1: SPI MODULE BLOCK DIAGRAM SCKx SSx Sync Control Control Clock SDOx bit 0 SDIx SPIxSR Transfer ...
Page 137
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 14-2: SPI MASTER/SLAVE CONNECTION PROCESSOR 1 (SPI Master) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (SPIxTXB) SPI Buffer (2) (SPIxBUF) (MSTEN (SPIxCON1<5> Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...
Page 138
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 14-5: SPI SLAVE AND FRAME MASTER CONNECTION DIAGRAM PIC24H FIGURE 14-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24H EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK TABLE 14-1: SAMPLE SCKx FREQUENCIES MHz CY Primary Prescaler Settings ...
Page 139
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 140
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 141
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) ...
Page 142
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 143
... C) Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. 2 The Inter-Integrated Circuit (I C) module provides complete hardware support for both Slave and Multi- ...
Page 144
... PIC24HJ32GP202/204 and PIC24HJ16GP304 2 FIGURE 15-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70289A-page 142 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...
Page 145
... PIC24HJ32GP202/204 and PIC24HJ16GP304 2 15 Module Addresses The 10-bit I2CxADD register contains the Slave mode addresses. If the A10M bit (I2CxCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received compared to the seven Least Significant bits of the I2CxADD register. ...
Page 146
... PIC24HJ32GP202/204 and PIC24HJ16GP304 15.11 Slope Control 2 The I C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user application to disable slew rate control if desired necessary to disable the slew rate control for 1 MHz mode. ...
Page 147
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module ...
Page 148
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit ...
Page 149
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0 HS R/C-0 HS R-0 HSC IWCOL I2COV D_A bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 150
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 151
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 152
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 150 Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... I/O modules avail- able in the PIC24HJ32GP202/204 PIC24HJ16GP304 device family. The UART is a full- duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA encoder and decoder ...
Page 154
... PIC24HJ32GP202/204 and PIC24HJ16GP304 16.1 UART Baud Rate Generator The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The BRGx register controls the period of a free-running 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: ...
Page 155
... PIC24HJ32GP202/204 and PIC24HJ16GP304 16.2 Transmitting in 8-bit Data Mode 1. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the BRGx register. c) Set up transmit and receive interrupt enable and priority bits. 2. Enable the UART. 3. Set the UTXEN bit (causes a transmit interrupt). ...
Page 156
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 16-1: UxMODE: UART R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 157
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 16-1: UxMODE: UART bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits ...
Page 158
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 16-2: U STA: UART x R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 159
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 16-2: U STA: UART x bit 4 RIDLE: Receiver Idle bit (read-only Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only Parity error has been detected for the current character (character at the top of the receive FIFO Parity error has not been detected ...
Page 160
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 158 Preliminary © 2007 Microchip Technology Inc. ...
Page 161
... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for fur- ther details. A block diagram of ADC for PIC24HJ16GP304 and PIC24HJ32GP204 devices is shown in Figure 17-1. A block diagram of the ADC for the PIC24HJ32GP202 device is shown in Figure 17-2. ...
Page 162
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 17-1: ADC1 MODULE BLOCK DIAGRAM FOR PIC24HFJ16GP304 AND PIC24HJ32GP204 DEVICES ( REF ( REF AN0 AN0 AN3 AN6 AN9 V REF AN1 AN1 AN4 AN7 AN10 V REF AN2 AN2 AN5 AN8 AN11 V REF 00000 00001 00010 00011 AN3 00100 AN4 ...
Page 163
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 17-2: ADC1 MODULE BLOCK DIAGRAM FOR PIC24HJ32GP202 DEVICES ( REF ( REF AN0 AN0 AN3 AN9 V REF AN1 AN1 AN4 AN10 V REF AN2 AN2 AN5 AN11 V REF 00000 00001 00010 00011 AN3 00100 AN4 00101 AN5 01001 AN9 01010 ...
Page 164
... PIC24HJ32GP202/204 and PIC24HJ16GP304 EQUATION 17-1: ADC CONVERSION CLOCK PERIOD FIGURE 17-3: ADC TRANSFER FUNCTION (10-BIT EXAMPLE) Output Code 11 1111 1111 (= 1023) 11 1111 1110 (= 1022) 10 0000 0011 (= 515) 10 0000 0010 (= 514) 10 0000 0001 (= 513) 10 0000 0000 (= 512) 01 1111 1111 (= 511) 01 1111 1110 (= 510) ...
Page 165
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 ADON — ADSIDL bit 15 R/W-0 R/W-0 R/W-0 SSRC<2:0> bit 7 Legend Cleared by hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating ...
Page 166
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘ ...
Page 167
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG<2:0> bit 15 R-0 U-0 R/W-0 BUFS — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ A 000 ...
Page 168
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock ...
Page 169
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ32GP204 and PIC24HJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 170
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ32GP204 and PIC24HJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 171
... Channel 0 negative input is AN1 0 = Channel 0 negative input is V bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits PIC24HJ32GP204 and PIC24HJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 ...
Page 172
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits PIC24HJ32GP204 and PIC24HJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 173
... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 CSS<12:0>: ADC Input Scan Selection bits ...
Page 174
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 172 Preliminary © 2007 Microchip Technology Inc. ...
Page 175
... PIC24HJ32GP202/204 and PIC24HJ16GP304 18.0 SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. PIC24HJ32GP202/204 and PIC24HJ16GP304 devices include several features that are intended to maximize application flexibility and reliability, and mini- mize cost through elimination of external components ...
Page 176
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 18-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS DESCRIPTION Bit Field Register BWRP FBS BSS<2:0> FBS BSS<2:0> FBS GSS<1:0> FGS GWRP FGS IESO FOSCSEL FNOSC<2:0> FOSCSEL DS70289A-page 174 Description Boot Segment Program Flash Write Protection 1 = Boot segment may be written ...
Page 177
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 18-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register FCKSM<1:0> FOSC IOL1WAY FOSC OSCIOFNC FOSC POSCMD<1:0> FOSC FWDTEN FWDT WINDIS FWDT WDTPRE FWDT WDTPOST<3:0> FWDT ALTI2C FPOR FPWRT<2:0> FPOR © 2007 Microchip Technology Inc. Description ...
Page 178
... To simplify system design, all devices in the PIC24HJ32GP202/204 PIC24HJ16GP304 family incorporate an on-chip regu- lator that allows the device to run its core logic from The regulator provides power to the core from the other V pins ...
Page 179
... PIC24HJ32GP202/204 and PIC24HJ16GP304 18.4 Watchdog Timer (WDT) For PIC24HJ32GP202/204 and PIC24HJ16GP304 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 18.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
Page 180
... Detailed information on this interface will be provided in future revisions of the document. 18.6 Code Protection and CodeGuard™ Security The PIC24HJ32GP202/204 and PIC24HJ16GP304 product families offer the intermediate implementation of CodeGuard Security. CodeGuard Security allows multiple parties to securely share resources (memory, TABLE 18-3: ...
Page 181
... PIC24HJ32GP202/204 and PIC24HJ16GP304 18.7 In-Circuit Serial Programming PIC24HJ32GP202/204 and PIC24HJ16GP304 family microcontrollers can be serially programmed while in the end application circuit. This is done with two lines for clock and data, and three other lines for power, ground and the programming sequence. Serial pro- ...
Page 182
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 180 Preliminary © 2007 Microchip Technology Inc. ...
Page 183
... INSTRUCTION SET SUMMARY Note: This data sheet summarizes the features of this group of PIC24HJ32GP202/204 and PIC24HJ16GP304 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. The PIC24H instruction set is identical to that of the PIC24F, and is a subset of the dsPIC30F/33F instruction set ...
Page 184
... PIC24HJ32GP202/204 and PIC24HJ16GP304 All instructions are single word. Ceratian of them were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is exe- cuted as an instruction (by itself), it will execute as a NOP ...
Page 185
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field One of 16 destination working registers ∈ {W0..W15} Wnd One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ ...
Page 186
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 19-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD f ADD ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG AND #lit10,Wn AND ...
Page 187
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 12 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb 13 BTSTS BTSTS f,#bit4 BTSTS.C Ws,#bit4 BTSTS.Z Ws,#bit4 14 CALL CALL lit23 CALL Wn 15 CLR CLR f CLR ...
Page 188
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 35 INC INC f INC f,WREG INC Ws,Wd 36 INC2 INC2 f INC2 f,WREG INC2 Ws,Wd 37 IOR IOR f IOR f,WREG IOR #lit10,Wn IOR Wb,Ws,Wd IOR Wb,#lit5,Wd 38 LNK LNK #lit14 39 LSR ...
Page 189
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 47 RCALL RCALL Expr RCALL Wn 48 REPEAT REPEAT #lit14 REPEAT Wn 49 RESET RESET 50 RETFIE RETFIE 51 RETLW RETLW #lit10,Wn 52 RETURN RETURN 53 RLC RLC f RLC f,WREG RLC Ws,Wd 54 RLNC ...
Page 190
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 TBLRDL TBLRDL Ws,Wd 67 TBLWTH TBLWTH Ws,Wd 68 TBLWTL TBLWTL Ws,Wd 69 ULNK ULNK 70 XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd DS70289A-page 188 Description Read Prog<15:0> Write Ws< ...
Page 191
... PIC24HJ32GP202/204 and PIC24HJ16GP304 20.0 DEVELOPMENT SUPPORT ® The PIC microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment ® - MPLAB IDE Software • Assemblers/Compilers/Linkers - MPASM Assembler TM - MPLAB C18 and MPLAB C30 C Compilers - MPLINK Object Linker/ ...
Page 192
... PIC24HJ32GP202/204 and PIC24HJ16GP304 20.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object ® files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 193
... PIC24HJ32GP202/204 and PIC24HJ16GP304 20.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB ...
Page 194
... PIC24HJ32GP202/204 and PIC24HJ16GP304 20.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins ...
Page 195
... This section provides an overview of PIC24HJ32GP202/204 and PIC24HJ16GP304 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24HJ32GP202/204 and PIC24HJ16GP304 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied ...
Page 196
... PIC24HJ32GP202/204 and PIC24HJ16GP304 21.1 DC Characteristics TABLE 21-1: OPERATING MIPS VS. VOLTAGE V Range DD Characteristic (in Volts) 3.0-3.6V 3.0-3.6V TABLE 21-2: THERMAL OPERATING CONDITIONS Rating Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Extended Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range ...
Page 197
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 21-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. Operating Voltage DC10 Supply Voltage V DD DC12 V RAM Data Retention Voltage DR DC16 V V Start Voltage POR DD to ensure internal Power-on Reset signal DC17 S V Rise Rate VDD DD to ensure internal ...
Page 198
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC20d 24 30 DC20a 27 30 DC20b 27 30 DC20c 27 35 DC21d 30 40 DC21a 37 40 DC21b 32 45 DC21c 33 45 DC22d 35 50 DC22a 38 50 DC22b 38 55 DC22c 39 55 DC23d ...
Page 199
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 21-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. Idle Current (I ): Core OFF Clock ON Base Current IDLE DC40d 3 25 DC40a 3 25 DC40b 3 25 DC40c 3 25 DC41d 4 25 DC41a 4 25 DC41b 5 25 DC41c 5 25 DC42d 6 25 DC42a 6 25 ...
Page 200
... PIC24HJ32GP202/204 and PIC24HJ16GP304 TABLE 21-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60d 55 500 DC60a 63 500 DC60b 85 500 DC60c 146 1 DC61d 8 12 DC61a 10 15 DC61b 12 20 DC61c 13 25 Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. ...