PIC18LF46J11-I/ML Microchip Technology, PIC18LF46J11-I/ML Datasheet - Page 372
![IC PIC MCU FLASH 64K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF46J11-I/ML
Manufacturer Part Number
PIC18LF46J11-I/ML
Description
IC PIC MCU FLASH 64K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18LF46J11-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 372 of 528
- Download datasheet (8Mb)
PIC18F46J11 FAMILY
23.6
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
TABLE 23-1:
DS39932C-page 372
HLVDCON
INTCON
PIR2
PIE2
IPR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
Name
Operation During Sleep
VDIRMAG
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIF
OSCFIE
OSCFIP
Bit 7
REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
BGVST
CM1IF
CM1IE
CM1IP
Bit 6
CM2IE
CM2IP
IRVST
CM2IF
Bit 5
HLVDEN
INT0IE
Bit 4
—
—
—
HLVDL3
23.7
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
BCLIE
BCLIP
BCLIF
RBIE
Bit 3
Effects of a Reset
HLVDL2
TMR0IF
LVDIF
LVDIE
LVDIP
Bit 2
HLVDL1
TMR3IE
TMR3IP
TMR3IF
INT0IF
© 2009 Microchip Technology Inc.
Bit 1
HLVDL0
CCP2IF
CCP2IE
CCP2IP
RBIF
Bit 0
on page
Values
Reset
63
65
65
65
66
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