PIC18LF46J11-I/ML Microchip Technology, PIC18LF46J11-I/ML Datasheet - Page 134
![IC PIC MCU FLASH 64K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF46J11-I/ML
Manufacturer Part Number
PIC18LF46J11-I/ML
Description
IC PIC MCU FLASH 64K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18LF46J11-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 134 of 528
- Download datasheet (8Mb)
PIC18F46J11 FAMILY
TABLE 9-5:
DS39932C-page 134
RB4/PMA1/
KBI0/RP7
RB5/PMA0/
KBI1/RP8
RB6/KBI2/
PGC/RP9
RB7/KBI3/
PGD/RP10
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
3:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
All other pin functions are disabled when ICSP™ or ICD are enabled.
This bit is not available on 28-pin devices.
PORTB I/O SUMMARY (CONTINUED)
Function
PMA1
PMA0
RP10
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB4
RP7
RB5
RP8
RB6
RP9
RB7
(3)
(3)
Setting
TRIS
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
x
1
0
0
1
1
x
x
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 7 input.
Remappable peripheral pin 7 output.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is
cleared.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 8 input.
Remappable peripheral pin 8 output.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD
operation.
Remappable peripheral pin 9 input.
Remappable peripheral pin 9 output.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Remappable peripheral pin 10 input.
Remappable peripheral pin 10 output.
(2)
Description
© 2009 Microchip Technology Inc.
(1)
(2)
(2)
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