PIC18LF46J11-I/ML Microchip Technology, PIC18LF46J11-I/ML Datasheet - Page 339
![IC PIC MCU FLASH 64K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF46J11-I/ML
Manufacturer Part Number
PIC18LF46J11-I/ML
Description
IC PIC MCU FLASH 64K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18LF46J11-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 339 of 528
- Download datasheet (8Mb)
19.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 19-13:
© 2009 Microchip Technology Inc.
RC6/TX1/CK1/RP17
RC6/TX1/CK1/RP17
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
pin (TXCKP = 0)
pin (TXCKP = 1)
SDO1/RP18 pin
RC7/RX1/DT1/
to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
(Interrupt)
RCREG1
CREN bit
RC1IF bit
bit SREN
SREN bit
Write to
EUSART SYNCHRONOUS MASTER
RECEPTION
Read
Q2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
bit 3
PIC18F46J11 FAMILY
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
Ensure bits, CREN and SREN, are clear.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RCxIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCxIE, was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
bit 5
bit 6
DS39932C-page 339
bit 7
Q1 Q2 Q3 Q4
‘0’
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