PIC24FJ32GB002-I/SO Microchip Technology, PIC24FJ32GB002-I/SO Datasheet - Page 251

• Manufacturer Part Number: PIC24FJ32GB002-I/SO
• Description: IC MCU 16BIT 32KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GB002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240019, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.0
FIGURE 21-1:
FIGURE 21-2:
© 2009 Microchip Technology Inc.
Note:
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
Shift Buffer
Data
32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
2: Polynomial length n is determined by ([PLEN<3:0>] + 1).
2 * F
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Section 30. “Programmable Cyclic
Redundancy Check (CRC)” (DS39714).
CY
Shift Clock
Family
CRC BLOCK DIAGRAM
CRC SHIFT ENGINE DETAIL
Bit 0
Reference
Read/Write Bus
CRCWDATH
CRCDATH
(4x32, 8x16 or 16x8)
CRC Shift Engine
X(1)
Manual”,
Variable FIFO
Shift Buffer
(1)
CRCWDATH
0
PIC24FJ64GB004 FAMILY
Preliminary
1
Bit 1
CRCWDATL
CRCDATL
LENDIAN
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable Interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in Figure 21-1. A simple version of the CRC shift
engine is shown in Figure 21-2.
up to 32 bits
X(2)
Shift Complete Event
FIFO Empty Event
(1)
Bit 2
CRCWDATL
CRCISEL
1
0
X(n)
Set CRCIF
(1)
DS39940C-page 249
Bit n
(2)