PIC16LF872-I/SP Microchip Technology, PIC16LF872-I/SP Datasheet - Page 101

• Manufacturer Part Number: PIC16LF872-I/SP
• Description: IC MCU FLASH 2KX14 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF872-I/SP

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 22
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped, for example, by
execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
FIGURE 11-10:
TABLE 11-7:
© 2006 Microchip Technology Inc.
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
Address
Note:
Config. bits
OPTION_REG
PSA and PS2:PS0 are bits in the OPTION_REG register.
Name
SUMMARY OF WATCHDOG TIMER REGISTERS
WDT Timer
Enable Bit
WATCHDOG TIMER BLOCK DIAGRAM
WDT
From TMR0 Clock Source
(Figure 5-1)
RBPU
Bit 7
(1)
BODEN
INTEDG
Bit 6
0
1
PSA
M
U
X
(1)
T0CS
Bit 5
CP1
0
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
T0SE
Bit 4
CP0
Time-out
8 - to - 1 MUX
MUX
Note 1: The CLRWDT and SLEEP instructions
WDT
Postscaler
2: When a CLRWDT instruction is executed
1
PWRTE
8
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
Bit 3
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
PSA
PSA
(1)
To TMR0 (Figure 5-1)
WDTE
PS2:PS0
Bit 2
PS2
PIC16F872
FOSC1
Bit 1
PS1
DS30221C-page 99
FOSC0
Bit 0
PS0