PIC16LF872-I/SP Microchip Technology, PIC16LF872-I/SP Datasheet
PIC16LF872-I/SP
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PIC16LF872-I/SP Summary of contents
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... Microchip Technology Inc. M 28-Pin, 8-Bit CMOS FLASH Microcontroller with 10-Bit A/D PIC16F872 Data Sheet DS30221B ...
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... Serialized Quick Term Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... Wide operating voltage range: 2.0V to 5.5V • Fully static design • Commercial, Industrial and Extended temperature ranges • Low power consumption: - < typical @ 5V, 4 MHz - 20 A typical @ 3V, 32 kHz - < typical standby current 2002 Microchip Technology Inc. PIC16F872 with 10-bit A/D Pin Diagram DIP, SOIC, SSOP MCLR/V PP RA0/AN0 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30221B-page 2 2002 Microchip Technology Inc. ...
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... Timers Capture/Compare/PWM module Serial Communications 10-bit Analog-to-Digital Module Instruction Set Packaging 2002 Microchip Technology Inc. PIC16F872 document to this data sheet, and is highly recom- mended reading for a better understanding of the device architecture and operation of the peripheral modules. The block diagram of the PIC16F872 architecture is shown in Figure 1-1 ...
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... Brown-out Reset In-Circuit Debugger Timer2 Synchronous 10-bit A/D Serial Port PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 2002 Microchip Technology Inc. ...
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... Not used TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 2002 Microchip Technology Inc. Buffer Description Type ST/CMOS Oscillator crystal or external clock input. ...
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... C mode). ST Digital I/O. SPI Data Out pin (SPI mode). ST Digital I/O. ST Digital I/O. — Ground reference for logic and I/O pins. — Positive supply for logic and I/O pins. I/O = input/output ST = Schmitt Trigger input 2 C mode power 2002 Microchip Technology Inc. ...
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... Reset Vector Interrupt Vector On-Chip Page 0 Program Memory 2002 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. ...
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... PCLATH 18Ah 10Bh INTCON 18Bh 10Ch EECON1 18Ch 10Dh EECON2 18Dh (1) 10Eh Reserved 18Eh (1) 10Fh 18Fh Reserved 110h 190h 1A0h 120h accesses A0h - BFh 1BFh 1C0h 16Fh 1EFh 170h 1F0h accesses 70h-7Fh 17Fh 1FFh Bank 3 2002 Microchip Technology Inc. ...
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... These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear. 2002 Microchip Technology Inc. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section ...
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... SEN 0000 0000 54, 94 1111 1111 43, 94 0000 0000 58 0000 0000 52, 94 — — — — — — — — — — — — — — — — — — xxxx xxxx 84, 94 PCFG1 PCFG0 80, 94 0--- 0000 2002 Microchip Technology Inc. ...
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... Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear. 2002 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 R/W-x RP0 Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W bit Bit is unknown 2002 Microchip Technology Inc. ...
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... When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper- ation of the device 2002 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer ...
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... R/W-0 R/W-0 R/W-0 R/W-0 TMR0IE INTE RBIE TMR0IF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-x INTF RBIF bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 ...
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... R/W-0 R/W-0 R/W-0 R/W-0 reserved reserved SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2002 Microchip Technology Inc. ...
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... BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt bit 2-1 Unimplemented: Read as '0' bit 0 Reserved: Always maintain this bit clear Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. U-0 R/W-0 R/W-0 U-0 — EEIE BCLIE — Writable bit U = Unimplemented bit, read as ‘ ...
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... U-0 R/W-0 R/W-0 U-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 R/W-0 — — reserved bit Master mode x = Bit is unknown 2002 Microchip Technology Inc. ...
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... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don’ ...
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... POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH regis- ter for any subsequent subroutine calls or GOTO instructions. Therefore, manipulation of the 2002 Microchip Technology Inc. ...
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... Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-2. 2002 Microchip Technology Inc. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: MOVLW 0x20 MOVWF FSR NEXT CLRF INCF ...
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... PIC16F872 NOTES: DS30221B-page 22 2002 Microchip Technology Inc. ...
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... EEDATH • EEADR • EEADRH • EECON1 • EECON2 2002 Microchip Technology Inc. PIC16F872 The EEPROM Data memory allows byte read and write operations without interfering with the normal operation of the microcontroller. When interfacing to EEPROM Data memory, the EEADR register holds the address to be accessed ...
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... MCLR Reset or WDT Time-out Reset during normal operation. U-0 U-0 U-0 R/W-x — — — WRERR R = Readable bit ’0’ = Bit is cleared location pointed to by R/W-0 R/S-0 R/S-0 WREN WR RD bit Writable bit - n = Value at POR x = Bit is unknown 2002 Microchip Technology Inc. ...
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... BSF INTCON, GIE BCF EECON1, WREN 2002 Microchip Technology Inc. should be kept clear at all times, except when writing to the EEPROM Data. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they both cannot be set in the same operation. The WREN bit should then be cleared by firmware after the write ...
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... These instructions must then be followed by two NOP instructions to allow the microcon- troller to setup for the write operation. Once the write is complete, the execution of instructions starts with the instruction after the second NOP. 2002 Microchip Technology Inc. ...
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... This should be used in applications where excessive writes can stress bits near the speci- fied endurance limits. 2002 Microchip Technology Inc. • Write AAh to EECON2 in two steps (first to W, then to EECON2) • Set the WR bit 7 ...
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... INTF RBIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu WR RD x--- x000 x--- u000 — — — (1) -r-0 0--r -r-0 0--r — (1) -r-0 0--r -r-0 0--r 2002 Microchip Technology Inc. ...
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... MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6>are always ; read as ’0’. 2002 Microchip Technology Inc. PIC16F872 FIGURE 4-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Data Latch Bus Port CK Q ...
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... Input/output or slave select input for synchronous serial port or analog input. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 PORTA Data Direction Register — — PCFG3 PCFG2 PCFG1 PCFG0 Value on: Value on all Bit 0 POR, other BOR RESETS RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 --0- 0000 --0- 0000 2002 Microchip Technology Inc. ...
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... PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). 2002 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the ...
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... Bit 3 Bit 2 Bit 1 Bit 0 RB6 RB5 RB4 RB3 RB2 INTEDG T0CS T0SE PSA PS2 Value on: Value on POR, all other BOR RESETS RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS1 PS0 1111 1111 1111 1111 2002 Microchip Technology Inc. ...
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... Peripheral Input Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. 2002 Microchip Technology Inc. FIGURE 4-6: Port/Peripheral Select Peripheral Data Out Data Bus WR PORT WR TRIS ...
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... Input/output port pin or Synchronous Serial Port data output (SPI mode). Input/output port pin. Input/output port pin. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 mode). Value on: Value on Bit 0 POR, all other BOR RESETS RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2002 Microchip Technology Inc. ...
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... Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). 2002 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...
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... R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2002 Microchip Technology Inc. ...
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... Timer0 Module Register 0Bh,8Bh, INTCON GIE 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS Legend unknown unchanged unimplemented locations read as ’0’. Shaded cells are not used by Timer0. 2002 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PEIE TMR0IE INTE RBIE TMR0IF INTF T0SE ...
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... PIC16F872 NOTES: DS30221B-page 38 2002 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). ...
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... The pres- caler, however, will continue to increment. 0 TMR1L 1 TMR1ON T1SYNC On/Off 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Synchronized Clock Input Synchronize det 2 Q Clock 2002 Microchip Technology Inc. ...
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... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. 2002 Microchip Technology Inc. PIC16F872 TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR ...
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... SSPIE CCP1IE TMR2IE TMR1IE Value on: Value on Bit 1 Bit 0 POR, all other BOR RESETS INTF RBIF 0000 000x 0000 000u TMR1IF r0rr 0000 0000 0000 r0rr 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2002 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Register 7-1 shows the Timer2 Control register. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). FIGURE 7-1: Sets Flag ...
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... SSPIE CCP1IE Value on: Value on Bit 1 Bit 0 POR, all other BOR RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 r0rr 0000 TMR2IE TMR1IE 0000 0000 r0rr 0000 0000 0000 0000 0000 1111 1111 1111 1111 2002 Microchip Technology Inc. ...
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... CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. Additional information on CCP modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) and in Application Note (AN594), “Using the CCP Modules” (DS00594). ...
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... EXAMPLE 8-1: CLRF CCP1CON MOVLW NEW_CAPT_PS ; Load the W reg with CCPR1L MOVWF CCP1CON TMR1L CHANGING BETWEEN CAPTURE PRESCALERS ; Turn CCP module off ; the new prescaler ; move value and CCP ON ; Load CCP1CON with this ; value 2002 Microchip Technology Inc. ...
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... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits are reserved; always maintain clear. 2002 Microchip Technology Inc. 8.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC<2> bit. ...
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... Resolution Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. • OSC (TMR2 prescale value) T • (TMR2 prescale value) OSC OSC log F PWM = bits log(2) 2002 Microchip Technology Inc. ...
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... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: These bits are reserved; always maintain clear. 2002 Microchip Technology Inc. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON ...
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... PIC16F872 NOTES: DS30221B-page 50 2002 Microchip Technology Inc. ...
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... I C modes are covered in Section 9.2, while special considerations for connect- 2 ing the I C bus are discussed in Section 9.3. 2002 Microchip Technology Inc. PIC16F872 The MSSP module is controlled by three special func- tion registers: • SSPSTAT • SSPCON • ...
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... Value at POR DS30221B-page 52 R-0 R-0 R-0 CKE D specs 2 C mode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2002 Microchip Technology Inc. ...
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... C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled 1001, 1010, 1100, 1101 = reserved Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 2 ...
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... C Master mode only Master mode only Master mode only Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 RSEN SEN bit 0 C module is not in the IDLE x = Bit is unknown 2002 Microchip Technology Inc. ...
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... Register ADCON1 must be set in a way that pin RA5 is configured as a digital I/O Any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (TRIS) register to the opposite value. 2002 Microchip Technology Inc. PIC16F872 FIGURE 9-1: MSSP BLOCK DIAGRAM (SPI MODE) ...
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... Note 1: When the SPI module is in Slave mode with (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set the SPI is used in Slave mode with CKE = '1', then SS pin control must be enabled. bit2 bit1 bit0 bit0 bit0 SS pin control enabled . DD 2002 Microchip Technology Inc. ...
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... SSPOV SSPEN CKP SSPM3 94h SSPSTAT SMP CKE Legend unknown unchanged unimplemented, read as ’0’. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are reserved; always maintain these bits clear. 2002 Microchip Technology Inc. bit6 bit5 bit3 bit4 bit2 bit5 ...
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... Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register opera modes to be selected mode, the SCL and SDA pins 2 C mode by setting the 2 C mode. Pull-up resis module. 2002 Microchip Technology Inc. ...
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... For a 10-bit address the first byte would equal ‘1111 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7-9 for slave transmitter: 2002 Microchip Technology Inc. PIC16F872 1. Receive first (high) byte of Address (bits SSPIF, BF and UA (SSPSTAT<1>) are set). ...
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... Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes Not Receiving Data ACK Bus Master terminates transfer ACK is not sent 2002 Microchip Technology Inc. ...
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... FIGURE 9-8: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE) General Call Address SDA SCL SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON<6>) GCEN (SSPCON2<7>) 2002 Microchip Technology Inc. R ACK SCL held low while CPU responds to SSPIF Cleared in software SSPBUF is written in software ...
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... Value on Bit 0 POR, all other BOR RESETS RBIF 0000 000x 0000 000u CCP2IF -r-0 0--0 -r-0 0--0 CCP2IE -r-0 0--r -r-0 0--r xxxx xxxx uuuu uuuu SEN 0000 0000 0000 0000 BF 0000 0000 0000 0000 2 C mode. 2002 Microchip Technology Inc. ...
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... This check is performed in hard- ware, with the result placed in the BCLIF bit. 2002 Microchip Technology Inc. The following events will cause the SSP Interrupt Flag bit, SSPIF set (an SSP Interrupt will occur if enabled): • ...
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... If Clock Arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 9-11). FIGURE 9-10: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPM3:SSPM0 Reload SCL Control CLKOUT SSPADD<6:0> Reload F /4 OSC BRG Down Counter 2002 Microchip Technology Inc. ...
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... SDA line held low, and the START condition is complete. FIGURE 9-12: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2002 Microchip Technology Inc. DX-1 SCL allowed to transition high BRG decrements (on Q2 and Q4 cycles) 02h 01h 00h (hold off) SCL is sampled high, reload takes place, and BRG starts its count ...
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... SSPCON2 is disabled until the Repeated START condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated START 1st Bit T BRG 2002 Microchip Technology Inc. ...
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... SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 2002 Microchip Technology Inc. PIC16F872 9.2.11.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out ...
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... PIC16F872 2 FIGURE 9-14 MASTER MODE TIMING (TRANSMISSION 10-BIT ADDRESS) DS30221B-page 68 2002 Microchip Technology Inc. ...
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... CPU, the BF flag is automati- cally cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). 2002 Microchip Technology Inc. PIC16F872 9.2.12.1 BF Status Flag In receive operation set when an address or data byte is loaded into SSPBUF from SSPSR ...
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... PIC16F872 2 FIGURE 9-15 MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS) DS30221B-page 70 2002 Microchip Technology Inc. ...
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... SCL is high, the P bit (SSPSTAT<4>) is set later, the PEN bit is cleared and the SSPIF bit is BRG set (Figure 9-17). 2002 Microchip Technology Inc. sampled high (clock arbitration), the baud rate genera- tor counts for T BRG lowing this, the ACKEN bit is automatically cleared, the ...
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... A RESET disables the SSP module and terminates the current transfer. SCL line sampled once every machine cycle (T Hold off BRG until SCL is sampled high BRG BRG 2 C module can receive SCL = 1, BRG starts counting clock high interval 4). OSC BRG 2002 Microchip Technology Inc. ...
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... Data changes while SCL = 0 SDA SCL BCLIF 2002 Microchip Technology Inc START, Repeated START, STOP or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- ...
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... SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SEN cleared automatically because of bus collision. SSP module reset into IDLE state. Set BCLIF. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software 2002 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA COLLISION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN ’0’ BCLIF S SSPIF 2002 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF ...
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... Repeated START condition is com- plete (Figure 9-23). Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG 2002 Microchip Technology Inc. ’0’ ’0’ Interrupt cleared in software ’0’ ’0’ ...
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... BCLIF P ’0’ ’0’ SSPIF 2002 Microchip Technology Inc. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> ...
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... I/O pins when 5V+10% and 2 C BUS V + 10% DD DEVICE must have one common supply line to which the pull-up resistor (5.5-0.4)/0.003 = p min , is shown in p for DD . Series s , due to the specified rise time mode (master or slave). C =10 - 400 pF b 2002 Microchip Technology Inc. ...
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... A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR 2002 Microchip Technology Inc. The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • ...
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... R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 AN0 C / HAN REF REF (1) RA0 Refs 8 RA3 RA3 RA3 RA3 RA2 6 6 RA3 V 5 RA3 RA2 4/2 A RA3 RA2 3/2 A RA3 RA2 2 1 RA3 RA2 1 Bit is unknown 2002 Microchip Technology Inc. ...
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... A/D BLOCK DIAGRAM A/D Converter V REF (Reference Voltage) V REF (Reference Voltage) 2002 Microchip Technology Inc. 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit 3. Wait the required acquisition time. 4. Start conversion: • ...
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... PICmicro™ (DS33023). ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD V DD Sampling Switch LEAKAGE V = 0.6V T ± 500 see ACQ Mid-Range Reference Manual SS C HOLD = DAC capacitance = 120 Sampling Switch (k ) 2002 Microchip Technology Inc. ...
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... When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom- mended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 14.1 and 14.2). 2002 Microchip Technology Inc. 10.3 Configuring Analog Port Pins The ADCON1, and TRIS registers control the operation of the A/D port pins ...
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... The extra bits are loaded with ’0’s’. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers. 10-Bit Result 0 7 ADRESH 10-bit Result and a maximum ADFM = 0000 00 ADRESL Left Justified 2002 Microchip Technology Inc. ...
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... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved; always maintain clear. 2002 Microchip Technology Inc. Turning off the A/D places the A/D module in its lowest current consumption state. Note: ...
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... PIC16F872 NOTES: DS30221B-page 86 2002 Microchip Technology Inc. ...
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... A set of configuration bits is used to select various options. Additional information on special features is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). 2002 Microchip Technology Inc. PIC16F872 11.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations ...
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... R = Readable bit - n = Value when device is unprogrammed DS30221B-page 88 (1) R/P-1 R/P-1 R/P-1 CPD LVP BODEN CP1 CP0 (2) (3) ( Programmable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state R/P-1 R/P-1 R/P-1 R/P-1 PWRTE WDTE F0SC1 F0SC0 bit0 2002 Microchip Technology Inc. ...
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... C2 Note 1: See Table 11-1 and Table 11-2 for recom- mended values of C1 and C2 series resistor (RS) may be required for AT strip cut crystals varies with the crystal chosen. 2002 Microchip Technology Inc. FIGURE 11-2: Clock from Ext. System TABLE 11-1: The Mode ...
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... DD R EXT ± 20 PPM ± 20 PPM C ± 50 PPM EXT ± 50 PPM V SS ± 30 PPM F OSC ± 30 PPM Recommended values: ® ) values, and the operat- EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC16F87X OSC2/CLKOUT / 100 k EXT C > 20pF EXT 2002 Microchip Technology Inc. ...
Page 93
... On-Chip 10-bit Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2002 Microchip Technology Inc. PIC16F872 SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situa- tions, as indicated in Table 11-4 ...
Page 94
... OSC — falls below V DD BOR BOR falls below V for less DD BOR rises above V . The DD BOR should fall DD , the Brown-out Reset pro- PWRT rises above V with the DD BOR Wake-up from Brown-out SLEEP 1024T OSC OSC 72 ms — 2002 Microchip Technology Inc. ...
Page 95
... Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 11-5 for RESET value for specific condition. 2002 Microchip Technology Inc. Program Counter 000h ...
Page 96
... Microchip Technology Inc. ...
Page 97
... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2002 Microchip Technology Inc. PIC16F872 DD T PWRT T OST T PWRT T OST VIA RC NETWORK) ): CASE 1 DD DS30221B-page 95 ...
Page 98
... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-8: SLOW RISETIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30221B-page 96 T PWRT VIA RC NETWORK PWRT T OST ): CASE OST 2002 Microchip Technology Inc. ...
Page 99
... TMR2IF TMR2IE TMR1IF TMR1IE BCLIF BCLIE 2002 Microchip Technology Inc. PIC16F872 The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the spe- cial function registers, PIR1 and PIR2. The correspond- ...
Page 100
... PIC16F872 devices, temporary holding registers, W_TEMP, STATUS_TEMP should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- text save and restore. The same code shown in Example 11-1 can be used. enable bit and PCLATH_TEMP, 2002 Microchip Technology Inc. ...
Page 101
... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 11-1 for operation of these bits. 2002 Microchip Technology Inc. WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- ues for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register ...
Page 102
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc- tion should be executed before a SLEEP instruction. 2002 Microchip Technology Inc. ...
Page 103
... To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/V RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. 2002 Microchip Technology Inc (2) T OST Interrupt Latency ...
Page 104
... For all other cases of low volt- age ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added but can IHH must be applied to the IHH on IHH 2002 Microchip Technology Inc. ...
Page 105
... A read operation is performed on a register even if the instruction writes to that register. 2002 Microchip Technology Inc. PIC16F872 For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB ...
Page 106
... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk Mid-Range MCU ™ 2002 Microchip Technology Inc. ...
Page 107
... Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2002 Microchip Technology Inc. BCF k Syntax: Operands: Operation: Status Affected: Description: BSF Syntax: f,d Operands: Operation: Status Affected: ...
Page 108
... W. If ’d’ the result is stored back in register ’f’. Decrement f [ label ] DECF f 127 d [0,1] ( (destination) Z Decrement register ’f’. If ’d’ the result is stored in the W register. If ’d’ the result is stored back in register ’f’. 2002 Microchip Technology Inc. ...
Page 109
... Status Affected: Z Description: The contents of register ’f’ are incremented. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. 2002 Microchip Technology Inc. PIC16F872 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 ...
Page 110
... None TOS PC, 1 GIE None Return with Literal label ] RETLW 255 k (W); TOS PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2002 Microchip Technology Inc. ...
Page 111
... The contents of register ’f’ are rotated one bit to the right through the Carry Flag. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. C Register f 2002 Microchip Technology Inc. PIC16F872 SLEEP Syntax: [ label ] SLEEP Operands: None Operation: ...
Page 112
... DS30221B-page 110 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2002 Microchip Technology Inc. f,d ...
Page 113
... A project manager • Customizable toolbar and key mapping • A status bar • On-line help 2002 Microchip Technology Inc. The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- matically updates all project information) • ...
Page 114
... ICEPIC In-Circuit Emulator The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards ...
Page 115
... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2002 Microchip Technology Inc. 13.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...
Page 116
... EE OQ Programming Tools K L evaluation and programming tools support EE OQ Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters. 2002 Microchip Technology Inc. ...
Page 117
... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16C8X PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers 2002 Microchip Technology Inc. PIC16F872 Kits Eval and Boards Demo DS30221B-page 115 ...
Page 118
... PIC16F872 NOTES: DS30221B-page 116 2002 Microchip Technology Inc. ...
Page 119
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. (except V , MCLR. and RA4) ......................................... -0. (Note 2) ...
Page 120
... PIC16F872 FIGURE 14-1: PIC16F872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V FIGURE 14-2: PIC16LF872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2 MHz Equation (6.0 MHz/V) (V MAX Equation (10.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro ...
Page 121
... DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) PIC16F872 (Commercial, Industrial) Param Symbol Characteristic/ No. Device V Supply Voltage DD D001 PIC16LF872 D001 PIC16F872 D001A PIC16LF872 D001A PIC16F872 D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on ...
Page 122
... PIC16F872 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) PIC16LF872 (Commercial, Industrial) PIC16F872 (Commercial, Industrial) Param Symbol Characteristic/ No. Device D015 I Brown-out BOR (6) Reset Current I Power-down Current PD D020 PIC16LF872 D020 PIC16F872 D021 PIC16LF872 D021 PIC16F872 D021A PIC16LF872 D021A PIC16F872 D023 I Brown-out ...
Page 123
... DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP modes) Ports RC3 and RC4: ...
Page 124
... PIC16F872 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output Low Voltage OL D080 I/O ports D083 OSC2/CLKOUT (RC osc config) V Output High Voltage OH (3) D090 I/O ports D092 OSC2/CLKOUT (RC osc config) V D150* V Open Drain High Voltage ...
Page 125
... This current should be added to the base When BOR is enabled, the device will operate correctly until the V 2002 Microchip Technology Inc. PIC16F872 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Min Typ† ...
Page 126
... DD V for V = 4 4. For entire V range DD V For entire V range (Note1 For entire V range DD V for V = 4 PIN SS A Vss PIN DD Pin at hi-impedance A Vss V V PIN DD A Vss XT, HS PIN DD and LP osc configuration 2002 Microchip Technology Inc. ...
Page 127
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2002 Microchip Technology Inc. PIC16F872 Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 128
... OSC2, but including PORTD and PORTE outputs as ports for OSC2 output DS30221B-page 126 specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load Condition Pin 2002 Microchip Technology Inc. ...
Page 129
... All devices are tested to operate at "Min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 2002 Microchip Technology Inc ...
Page 130
... Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ns (Note 1) 35 100 ns (Note 1) — 0. (Note 1) CY — — ns (Note 1) — — ns (Note 1) 100 255 ns — — ns — — ns — — — 145 — 145 ns — — ns — — ns 2002 Microchip Technology Inc. ...
Page 131
... T Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc. PIC16F872 BOR 35 Min Typ† ...
Page 132
... N = prescale value (2, 4,..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns Must also meet parameter 47 — ns — ns — ns — ns — prescale value ( prescale value ( — ns — ns 200 kHz 7T — OSC 2002 Microchip Technology Inc. ...
Page 133
... CCP1 Output Rise Time 54* TccF CCP1 Output Fall Time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc Min 0 ...
Page 134
... FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Note: Refer to Figure 14-3 for load conditions. DS30221B-page 132 MSb BIT6 - - - - - -1 75, 76 BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb LSb LSb 2002 Microchip Technology Inc. ...
Page 135
... Note: Refer to Figure 14-3 for load conditions. FIGURE 14-13: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 14-3 for load conditions. 2002 Microchip Technology Inc MSb BIT6 - - - - - -1 75, 76 MSb IN BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb IN PIC16F872 ...
Page 136
... STOP Condition Conditions ns Only relevant for Repeated START condition ns After this period, the first clock pulse is generated ns ns 2002 Microchip Technology Inc. ...
Page 137
... SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line: T max 1000 + 250 = 1250 ns (according to the standard mode DAT released. 2002 Microchip Technology Inc. 100 101 106 107 109 Min Max 100 kHz mode 4.0 — ...
Page 138
... PIC16F872 TABLE 14-9: A/D CONVERTER CHARACTERISTICS: PIC16F872 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LF872 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution R A03 E Integral Linearity Error IL A04 E Differential Linearity Error DL A06 E Offset Error OFF A07 E Gain Error GN A10 — Monotonicity A20 V Reference Voltage ( REF REF ...
Page 139
... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following T 2: See Section 10.1 for min. conditions. 2002 Microchip Technology Inc. (1) 131 130 8 ...
Page 140
... PIC16F872 NOTES: DS30221B-page 138 2002 Microchip Technology Inc. ...
Page 141
... Minimum: mean – 3 (-40°C to 125° . FIGURE 15-2: MAXIMUM Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) 7 Minimum: mean – 3 (-40°C to 125° . 2002 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC 3.5V 3. vs. F OVER V (HS MODE) OSC . ...
Page 142
... F (MHz) OSC vs. F OVER V (XT MODE) OSC DD 1.5 2.0 2.5 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.2V 3.0 3.5 4.0 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.2V 3.0 3.5 4.0 2002 Microchip Technology Inc. ...
Page 143
... FIGURE 15-6: MAXIMUM I DD 120 110 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 100 2002 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC (kHz) OSC vs. F OVER V (LP MODE) OSC (kHz) ...
Page 144
... DS30221B-page 142 vs. V FOR VARIOUS VALUES 3.3k 5.1k 10k 100k 3.5 4.0 V (V) DD vs. V FOR VARIOUS VALUES 3.3k 5.1k 10k 100k 3.5 4.0 V (V) DD 4.5 5.0 5.5 4.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 145
... MODE, ALL PERIPHERALS DISABLED 100 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125° 0.1 0.01 2.0 2.5 2002 Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.3k 5.1k 10k 100k 3.0 3.5 4.0 V (V) DD Max (125C) Max (125° ...
Page 146
... Typ (25°C) Typ (25C) 3.5 4.0 V (V) DD Note: Device current in RESET depends on oscillator mode, frequency and circuit. Device in SLEEP Device in Sleep Max SLEEP Max Sleep Typ SLEEP (25°C) Typ Sleep (25C) 4.5 5.0 5.5 4.5 5.0 5.5 2002 Microchip Technology Inc. ...
Page 147
... FIGURE 15-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs 2.0 2.5 3.0 2002 Microchip Technology Inc. PIC16F872 vs. V OVER TEMPERATURE WDT DD Max (125°C) Max (125C) Typ (25°C) Typ (25C) 3.5 4.0 4 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – ...
Page 148
... Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 3.0 3.5 4.0 V ( Max (-40°C) Max (-40C) Typ (25°C) Typ (25C) Min (125°C) Min (125C (-mA) OH 4.5 5.0 5.5 (V =5V, - +125 2002 Microchip Technology Inc. ...
Page 149
... Minimum: mean – 3 (-40°C to 125°C) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2002 Microchip Technology Inc. vs Max (-40°C) Max (-40C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Typ (25°C) ...
Page 150
... DS30221B-page 148 vs =3V, - +125 Max (125°C) Max (125C) Typ (25°C) Typ (25C) Min (-40°C) Min (-40C (-mA (TTL INPUT, - +125 Max Min 3.5 4.0 4 5.0 5.5 2002 Microchip Technology Inc. ...
Page 151
... Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 2002 Microchip Technology Inc. PIC16F872 vs. V (ST INPUT, - +125 Max High Min High Max Low Min Low 3.5 4.0 4 ...
Page 152
... PIC16F872 NOTES: DS30221B-page 150 2002 Microchip Technology Inc. ...
Page 153
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. PIC16F872 Example PIC16F872/SP 0117017 Example PIC16F872-I/SO 0110017 Example PIC16LF872 -I/SS 0120017 DS30221B-page 151 ...
Page 154
... MILLIMETERS MIN NOM MAX 28 2.54 3.56 3.81 4.06 3.18 3.30 3.43 0.38 7.62 7.87 8.26 6.99 7.24 7.49 34.16 34.67 35.18 3.18 3.30 3.43 0.20 0.29 0.38 1.02 1.33 1.65 0.41 0.48 0.56 8.13 8.89 10. 2002 Microchip Technology Inc. ...
Page 155
... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 2002 Microchip Technology Inc Units INCHES* ...
Page 156
... A2 MILLIMETERS* MIN NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0. 2002 Microchip Technology Inc. ...
Page 157
... Sheet (DS35008). B 12/01 Final version of data sheet. Includes DC and AC charac- teristics graphs and updated electrical specifications. 2002 Microchip Technology Inc. PIC16F872 APPENDIX B: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table B-1. ...
Page 158
... PIC16F872 NOTES: DS30221B-page 156 2002 Microchip Technology Inc. ...
Page 159
... I C Slave Mode ......................................................... 58 Interrupt Logic ............................................................ 97 MSSP (SPI Mode) ..................................................... 55 On-Chip Reset Circuit ................................................ 91 Peripheral Output Override (RC 2:0, 7:5) .................. 33 Peripheral Output Override (RC 4:3) ......................... 33 PIC16F872 .................................................................. 4 2002 Microchip Technology Inc. PWM Mode ............................................................... 48 RA3:RA0 and RA5 Pins ............................................ 29 RA4/T0CKI Pin .......................................................... 29 RB3:RB0 Pins ........................................................... 31 RB7:RB4 Pins ........................................................... 31 RC Oscillator Mode ................................................... 90 2 SSP (I C Master Mode) ...
Page 160
... ANDWF ................................................................... 105 BCF ......................................................................... 105 BSF ......................................................................... 105 BTFSC ..................................................................... 105 BTFSS ..................................................................... 105 CALL ....................................................................... 106 CLRF ....................................................................... 106 CLRW ...................................................................... 106 , 21 CLRWDT ................................................................. 106 COMF ...................................................................... 106 DECF ....................................................................... 106 DECFSZ .................................................................. 107 GOTO ...................................................................... 107 INCF ........................................................................ 107 INCFSZ ................................................................... 107 IORLW ..................................................................... 107 IORWF .................................................................... 107 , 101 , 101 , 102 , 21 2002 Microchip Technology Inc. ...
Page 161
... Evaluation and Programming Tools ................... 114 Load Conditions ............................................................... 126 Loading of PC .................................................................... 20 Low Voltage ICSP Programming ..................................... 102 Low Voltage In-Circuit Serial Programming ....................... 87 2002 Microchip Technology Inc. M Master Clear (MCLR) MCLR Reset, Normal Operation .........................91 MCLR Reset, SLEEP ..........................................91 Master Synchronous Serial Port. See MSSP MCLR/V Pin ..................................................................... 5 PP Memory Organization ...
Page 162
... PIR1 (Peripheral Interrupt Request 1) Register ........ 16 PIR2 (Peripheral Interrupt Request 2) Register ........ 18 Special Function, Summary ........................................ SSPCON (Sync Serial Port Control) Register ........... 53 SSPCON2 (Sync Serial Port Control 2) Register ...... 54 SSPSTAT (Sync Serial Port Status) Register ........... STATUS Register ...................................................... 12 T1CON (Timer1 Control) Register ............................. 39 T2CON (Timer 2 Control) Register ............................ 2002 Microchip Technology Inc. ...
Page 163
... SSPCON Register ............................................................... 9 SSPCON2 Register ........................................................... 10 SSPEN Bit ......................................................................... 53 SSPIF ......................................................................... 16 SSPM3:SSPM0 Bits .......................................................... 53 SSPOV Bit .................................................................. 53 SSPOV Status Flag ........................................................... 69 SSPSTAT Register ..................................................... 10 Stack .................................................................................. 20 Overflows ................................................................... 20 Underflow .................................................................. 20 2002 Microchip Technology Inc STATUS Register ..........................................................9 C Bit .......................................................................... 12 DC Bit ........................................................................ 12 IRP Bit ....................................................................... 12 PD Bit ..................................................................12 RP1:RP0 Bits ............................................................ 12 TO Bit ..................................................................12 Z Bit ........................................................................... 12 Synchronous Serial Port Enable Bit (SSPEN) ................... 53 Synchronous Serial Port Interrupt ...
Page 164
... Time-out Period ......................................................... 99 WDT Reset, Normal Operation ...........................91 WDT Reset, SLEEP ............................................91 WDT Reset, Wake-up ............................................... 93 WCOL ................................................................................ 65 WCOL Bit .......................................................................... 53 WCOL Status Flag ........................................ 65 Write Collision Detect Bit (WCOL) ..................................... 53 Write Verify , 133 Data EEPROM and FLASH Program Memory .......... 27 , 133 WWW, On-Line Support ...................................................... 100 , 2002 Microchip Technology Inc. ...
Page 165
... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2002 Microchip Technology Inc. PIC16F872 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...
Page 166
... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30221B-page 164 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS30221B 2002 Microchip Technology Inc. ...
Page 167
... Note PIC16F872 PIC16F872 - I/P 301 = Industrial temp., skinny PDIP package, normal V limits, QTP pattern DD #301. PIC16F872 - E/SO = Extended temp., SOIC package, normal V limits. DD PIC16LF872 - /SS = Commercial temp., SSOP package, extended V limits CMOS FLASH LF = Low Power CMOS FLASH tape and reel - SOIC, PLCC, MQFP, TQFP packages only ...
Page 168
... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 ...