DSPIC33FJ12MC202-I/SO Microchip Technology, DSPIC33FJ12MC202-I/SO Datasheet - Page 170

• Manufacturer Part Number: DSPIC33FJ12MC202-I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330021, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ12MC201/202
15.7.2
When the CPU is placed in Idle mode and the QEI mod-
ule is configured in 16-bit Timer mode, the 16-bit timer
will operate if QEISIDL (QEICON<13>) = 0. This bit
defaults to a logic ‘0’ upon executing POR. To halt the
timer module during CPU Idle mode, QEISIDL should
be set to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally as if CPU Idle mode had not been entered.
15.8
The Quadrature Encoder Interface can generate an
interrupt on occurrence of the following events:
• 16-bit up/down position counter rollover/underflow
• Detection of qualified index pulse
• CNTERR bit is set
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF in the IFS3 register, is
asserted upon occurrence of any of these events. The
QEIIF bit must be cleared in software.
Enabling an interrupt is accomplished via the
respective enable bit, QEIIE, in the IEC3 register.
DS70265B-page 168
Quadrature Encoder Interface
Interrupts
TIMER OPERATION DURING CPU
IDLE MODE
Preliminary
15.9
The QEI module has four user-accessible registers,
accessible in either Byte or Word mode:
• Control/Status Register (QEICON) – Allows
• Digital Filter Control Register (DFLTCON) –
• Position Count Register (POSCNT) – Allows
• Maximum Count Register (MAXCNT) – Holds a
control of the QEI operation and status flags
indicating the module state.
Allows control of the digital input filter operation.
reading and writing of the 16-bit position counter.
value that is compared to the POSCNT counter in
some operations.
Note:
Control and Status Registers
The
accesses,. However, reading the register
in Byte mode can result in partially
updated values in subsequent reads.
Either use Word mode reads/writes, or
ensure that the counter is not counting
during Byte operations.
POSCNT
© 2007 Microchip Technology Inc.
register
allows
byte