PIC16F872-I/SO Microchip Technology, PIC16F872-I/SO Datasheet - Page 76
![IC MCU FLASH 2KX14 EE 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F872-I/SO
Manufacturer Part Number
PIC16F872-I/SO
Description
IC MCU FLASH 2KX14 EE 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F872-ISO.pdf
(168 pages)
5.PIC16F872-ISO.pdf
(5 pages)
6.PIC16F872-ISO.pdf
(6 pages)
7.PIC16F872-ISO.pdf
(168 pages)
Specifications of PIC16F872-I/SO
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SPI/SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F872-I/SO
Manufacturer:
MICROCHI
Quantity:
470
Company:
Part Number:
PIC16F872-I/SO
Manufacturer:
TI
Quantity:
5
Part Number:
PIC16F872-I/SO
Manufacturer:
MIC
Quantity:
20 000
PIC16F872
9.2.18.1
During a START condition, a bus collision occurs if:
a)
b)
During a START condition, both the SDA and the SCL
pins are monitored. If either the SDA pin or the SCL pin
is already low, then these events all occur:
• the START condition is aborted,
• and the BCLIF flag is set
• and the SSP module is reset to its IDLE state
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 9-20:
DS30221C-page 74
(Figure 9-20).
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-20).
SCL is sampled low before SDA is asserted low.
(Figure 9-21).
Bus Collision During a START
Condition
BUS COLLISION DURING START CONDITION (SDA ONLY)
condition if SDA = 1, SCL=1
Set SEN, enable START
SDA sampled low before
START condition.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
Set BCLIF.
SSPIF and BCLIF are
cleared in software
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-22). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0. During this time, if the SCL pins are
sampled as '0', a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
SSPIF and BCLIF are
cleared in software
© 2006 Microchip Technology Inc.