PIC16CE625-04I/SO Microchip Technology, PIC16CE625-04I/SO Datasheet - Page 59

• Manufacturer Part Number: PIC16CE625-04I/SO
• Description: IC MCU OTP 2KX14 EE COMP 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE625-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1075 - ADAPTER 18-SOIC TO 18-SOICAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

10.5
The PIC16CE62X has 4 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PortB change interrupts (pins RB<7:4>)
• Comparator interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction,
interrupt routine, as well as sets the GIE bit, which
re-enable RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine, the source(s) of
FIGURE 10-15: INTERRUPT LOGIC
1999 Microchip Technology Inc.
Interrupts
CMIE
CMIF
INTF
INTE
PEIE
T0IE
RBIE
T0IF
RBIF
GIE
RETFIE
, exits
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on
(Figure 10-16). The latency is the same for one or two
cycle instructions. Once in the interrupt service routine
the source(s) of the interrupt can be determined by poll-
ing the interrupt flag bits. The interrupt flag bit(s) must
be cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
Note 1: Individual interrupt flag bits are set,
2:
regardless
corresponding mask bit or the GIE bit.
When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
when the interrupt event occurs
PIC16CE62X
Wake-up
(If in SLEEP mode)
of
Interrupt
to CPU
the
status
DS40182C-page 59
of
their