PIC16CE625-04I/SO Microchip Technology, PIC16CE625-04I/SO Datasheet - Page 14

• Manufacturer Part Number: PIC16CE625-04I/SO
• Description: IC MCU OTP 2KX14 EE COMP 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE625-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1075 - ADAPTER 18-SOIC TO 18-SOICAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PIC16CE62X
4.2.2
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
DS40182C-page 14
Address Name
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh-1Eh Unimplemented
1Fh
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-9Eh
90h
9Fh
Note 1:
Note 2:
Legend:
SPECIAL FUNCTION REGISTERS
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIR1
CMCON
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIE1
Unimplemented
PCON
Unimplemented
EEINTF
VRCON
Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.
IRP & RPI bits are reserved; always maintain these bits clear.
—
= Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
SPECIAL REGISTERS FOR THE PIC16CE62X
Addressing this location uses contents of FSR to address data memory (not a physical
register)
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Addressing this location uses contents of FSR to address data memory (not a physical
register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
C2OUT
TRISB7
RBPU
VREN
IRP
Bit 7
RB7
GIE
IRP
GIE
—
—
—
—
—
—
—
—
(2)
INTEDG
C1OUT
TRISB6
RP1
VROE
CMIE
CMIF
Bit 6
PEIE
PEIE
RB6
RP1
—
—
—
—
—
—
(2)
TRISB5
T0CS
Bit 5
T0IE
T0IE
VRR
RP0
RB5
RP0
—
—
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
Write buffer for upper 5 bits of program counter
TRISA4
TRISB4
T0SE
INTE
INTE
Bit 4
RA4
RB4
TO
TO
—
—
—
—
—
—
TRISA3
TRISB3
RBIE
RBIE
Bit 3
RA3
RB3
PSA
VR3
CIS
PD
PD
—
—
—
—
The special registers can be classified into two sets
(core and peripheral). The Special Function Registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
TRISA2
TRISB2
EESCL
Bit 2
T0IF
CM2
T0IF
RA2
RB2
PS2
VR2
—
—
—
Z
Z
TRISA1
TRISB1
EESDA
INTF
INTF
Bit 1
CM1
POR
RA1
RB1
PS1
VR1
DC
DC
—
—
TRISA0
TRISB0
EEV
Bit 0
RBIF
RBIF
BOD
CM0
RA0
RB0
PS0
VR0
—
—
C
C
DD
1999 Microchip Technology Inc.
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---x 0000
xxxx xxxx
---0 0000
0000 000x
-0-- ----
00-- 0000
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---0 0000
0000 000x
-0-- ----
---- --0x
---- -111
000- 0000
POR Reset
Value on
—
—
—
—
—
—
—
—
—
Value on all
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
---u 0000
uuuu uuuu
---0 0000
0000 000u
-0-- ----
00-- 0000
xxxx xxxx
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 1111
1111 1111
---0 0000
0000 000u
-0-- ----
---- --uq
---- -111
000- 0000
resets
other
—
—
—
—
—
—
—
—
—
(1)