ATMEGA16L-8MI Atmel, ATMEGA16L-8MI Datasheet - Page 121
![IC AVR MCU 16K 8MHZ IND 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA16L-8MI
Manufacturer Part Number
ATMEGA16L-8MI
Description
IC AVR MCU 16K 8MHZ IND 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16L-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 121 of 357
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Compare Match
Output Unit
Compare Output Mode
and Waveform
Generation
2466T–AVR–07/10
The Compare Output mode (COM21:0) bits have two functions. The Waveform Generator uses
the COM21:0 bits for defining the Output Compare (OC2) state at the next compare match. Also,
the COM21:0 bits control the OC2 pin output source.
the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the fig-
ure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT)
that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference
is for the internal OC2 Register, not the OC2 pin.
Figure 56. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC2) from the waveform
generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis-
ter bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the
pin. The port override function is independent of the Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC2 state before the out-
put is enabled. Note that some COM21:0 bit settings are reserved for certain modes of
operation.
The waveform generator uses the COM21:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no action on the OC2
Register is to be performed on the next compare match. For compare output actions in the non-
PWM modes refer to
and for phase correct PWM refer to
A change of the COM21:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2 strobe bits.
See “8-bit Timer/Counter Register Description” on page 128.
COMn1
COMn0
FOCn
clk
I/O
Table 51 on page
Waveform
Generator
Table 53 on page
129. For fast PWM mode, refer to
D
D
D
PORT
DDR
OCn
Q
Q
Q
Figure 56
129.
1
0
shows a simplified schematic of
ATmega16(L)
Table 52 on page
OCn
Pin
129,
121
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