ATMEGA16L-8MI Atmel, ATMEGA16L-8MI Datasheet - Page 120
![IC AVR MCU 16K 8MHZ IND 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA16L-8MI
Manufacturer Part Number
ATMEGA16L-8MI
Description
IC AVR MCU 16K 8MHZ IND 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16L-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 120 of 357
- Download datasheet (8Mb)
Force Output
Compare
Compare Match
Blocking by TCNT2
Write
Using the Output
Compare Unit
2466T–AVR–07/10
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled
the CPU will access the OCR2 directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2) bit. Forcing compare match will not set the
OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real compare match
had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the output compare unit, inde-
pendently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals
the OCR2 value, the compare match will be missed, resulting in incorrect waveform generation.
Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting.
The setup of the OC2 should be performed before setting the Data Direction Register for the port
pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare
(FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing
between Waveform Generation modes.
Be aware that the COM21:0 bits are not double buffered together with the compare value.
Changing the COM21:0 bits will take effect immediately.
ATmega16(L)
120
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