DSPIC30F2011-20I/SO Microchip Technology, DSPIC30F2011-20I/SO Datasheet
DSPIC30F2011-20I/SO
Specifications of DSPIC30F2011-20I/SO
Related parts for DSPIC30F2011-20I/SO
DSPIC30F2011-20I/SO Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance Digital Signal Controllers Preliminary DS70139C ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... High-Performance Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’ ...
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... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K Pin Diagrams 18-Pin PDIP and SOIC EMUD3/AN0/V EMUD3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 15 Preliminary DS70139C-page 3 ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0. DS70139C-page AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 19 CN17/RF4 dsPIC30F2012 4 18 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 Preliminary © 2005 Microchip Technology Inc. ...
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... Pin Diagram 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note: For descriptions of individual pins, see Section 1.0. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3012 Preliminary 33 OSC2/CLKO/RC15 32 OSC1/CLKI AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 DS70139C-page 5 ...
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... Pin Diagrams 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note: For descriptions of individual pins, see Section 1.0. DS70139C-page dsPIC30F3013 Preliminary OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 © 2005 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 7 ...
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... NOTES: DS70139C-page 8 Preliminary © 2005 Microchip Technology Inc. ...
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... The following block diagrams depict the architecture for these devices: • Figure 1-1 illustrates the dsPIC30F2011 • Figure 1-2 illustrates the dsPIC30F2012 • Figure 1-3 illustrates the dsPIC30F3012 • Figure 1-4 illustrates the dsPIC30F3013 Following the block diagrams, Table 1-1 relates the I/O functions to pinout information ...
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... FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (12 Kbytes) Data Latch 16 ROM Latch 24 16 Instruction Decode & Control Power-up ...
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... OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low Voltage Detect 12-bit ADC Capture Module © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (512 bytes) (512 bytes) 16 Address Address Latch Latch 16 16 ...
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... FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... Timing Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low Voltage Detect 12-bit ADC Capture Module © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch Latch RAGU ...
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... Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... REF Legend: CMOS = CMOS compatible input or output Analog Schmitt Trigger input with CMOS levelsO Input P © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Buffer Type ST Synchronous serial clock input/output for I ST Synchronous serial data input/output for I — 32 kHz low power oscillator crystal output. ...
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... NOTES: DS70139C-page 16 Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of ...
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... The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 ...
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... Divide Support The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF - 16/16 signed fractional divide 2 ...
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... EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139C-page 22 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2005 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When satu- ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70139C-page 26 Preliminary © 2005 Microchip Technology Inc. ...
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... Figure 3-1. The program space memory map for the dsPI30F3012/3013 is shown in Figure 3-2. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1 ...
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... FIGURE 3-1: dsPIC30F2011/2012 PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (4K instructions) Reserved (Read ‘0’s) Reserved UNITID (32 instr.) Reserved Device Configuration Registers Reserved DEVID (2) DS70139C-page 28 FIGURE 3-2: ...
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... Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24-bit wide program memory. Consequently, instructions are always However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3 ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the Programmer’s Reference Manual (DS70030) for details on instruction encoding. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn<0> ...
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... FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space 15 EA<15> Data Space 15 EA EA<15> Upper Half of Data Space is Mapped into Program Space BSET CORCON,#2 ; Set PSV bit MOV #0x0 Set PSVPAG register MOV W0, PSVPAG MOV 0x9200 Access program memory location ...
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... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in Figure 3-7. The data space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in Figure 3-8. ...
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... FIGURE 3-8: dsPIC30F3012/3013 DATA SPACE MEMORY MAP MS Byte Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 2 Kbyte 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70139C-page 34 LS Byte 16 bits Address MSB LSB 0x0000 SFR Space ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 Preliminary ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the stack pointer. SPLIM is uninitialized at Reset the case for the stack pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned ...
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... DS70139C-page 38 Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 39 ...
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... NOTES: DS70139C-page 40 Preliminary © 2005 Microchip Technology Inc. ...
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... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the effective address (EA) calculation associated with any W regis- ter important to realize that the address bound- aries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decre- menting buffers) boundary addresses (not just equal to) ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... NOTES: DS70139C-page 46 Preliminary © 2005 Microchip Technology Inc. ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... LOADING WRITE LATCHES Example 5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 5-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 51 ...
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... NOTES: DS70139C-page 52 Preliminary © 2005 Microchip Technology Inc. ...
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... Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software. They are cleared in hardware at the com- pletion of the write operation ...
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... Erasing Data EEPROM 6.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EXAMPLE 6-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV #data2,W2 TBLWTL W2 [ W0]++ , MOV #data3,W2 TBLWTL W2 [ W0]++ , MOV #data4,W2 TBLWTL W2 [ W0]++ , MOV #data5,W2 TBLWTL W2 [ W0]++ , MOV #data6,W2 TBLWTL W2 [ W0]++ , MOV #data7,W2 TBLWTL W2 [ W0]++ ...
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... WR Port Read LAT Read Port © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 59 ...
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... DS70139C-page 60 Preliminary © 2005 Microchip Technology Inc. ...
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... There are exter- nal signals (CN0 through CN7, CN17 and CN18) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 7-7: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2011/3012 (BITS 7-0) SFR Addr. Bit 7 Bit 6 ...
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... NOTES: DS70139C-page 62 Preliminary © 2005 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the con- trol and status flags for the processor exceptions ...
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... LVD - Low Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority * Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. Preliminary © 2005 Microchip Technology Inc. Interrupt Source 2 C Slave Interrupt 2 C Master Interrupt ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
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... The processor then loads the priority level for this inter- rupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x000002 0x0000 ...
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... Fast Context Saving A context saving option is available using shadow reg- isters. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 69 ...
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... DS70139C-page 70 Preliminary © 2005 Microchip Technology Inc. ...
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... SOSCO/ T1CK LPOSCEN SOSCI © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0) ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
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... DS70139C-page 74 Preliminary © 2005 Microchip Technology Inc. ...
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... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70139C-page 76 ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 TGATE ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 79 ...
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... NOTES: DS70139C-page 80 Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels. 11.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE - Input Capture Buffer Not Empty • ICOV - Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 83 ...
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... NOTES: DS70139C-page 84 Preliminary © 2005 Microchip Technology Inc. ...
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... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OC1CON and OC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have 2 compare channels. OCxRS and OCxR in Figure 12-1 represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 12.2 Simple Output Compare Match Mode When control bits OCM< ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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... DS70139C-page 88 Preliminary © 2005 Microchip Technology Inc. ...
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... It is useful for communicating with other peripheral devices, such as EEPROMs, shift registers, display drivers and A/D converters, or other microcontrollers compatible with Motorola's SPI and SIOP interfaces. The dsPIC30F2011/2012/3012/ 3013 devices feature one SPI module, SPI1. 13.1 Operating Function Description ...
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... Figure 13-2 depicts the a master/slave connection between two processors. In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPI1BUF. The interrupt is generated at the middle of the transfer of the last bit. In Slave mode, data is transmitted and received as external clock pulses appear on SCK ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 13.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPI1STAT< ...
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... DS70139C-page 92 Preliminary © 2005 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
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... FIGURE 14- BLOCK DIAGRAM Shift SCL Clock SDA Stop bit Detect Start, RESTART, Stop bit Generate Shift Clock DS70139C-page 94 I2CRCV I2CRSR LSB Addr_Match Match Detect I2CADD Start and Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down ...
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... SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
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... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 14.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 99
... When the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support As a master device, six operations are supported: ...
Page 100
... I C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (I2CCON<11>). The I module must be Idle before the RCEN bit is set, other- wise the RCEN bit will be disregarded. The baud rate generator begins counting and on each rollover, the state of the SCL pin ACK and data are shifted into the I2CRSR on the rising edge of each clock ...
Page 101
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 99 ...
Page 102
... NOTES: DS70139C-page 100 Preliminary © 2005 Microchip Technology Inc. ...
Page 103
... Family Reference Manual (DS70046). This section describes the Universal Asynchronous Receiver/Transmitter Communications module. The dsPIC30F2011/2012/3012 processors have one UART module (UART1). The dsPIC30F3013 processor has two UART modules (UART1 and UART2). FIGURE 15-1: UART TRANSMITTER BLOCK DIAGRAM ...
Page 104
... FIGURE 15-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70139C-page 102 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 106
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 107
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode in which a 9th bit (URX8) value of ‘ ...
Page 108
... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input (IC1 for UART1 and IC2 for UART2). To enable this mode, you must program the input capture module to detect the falling and rising edges of the Start bit ...
Page 109
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139C-page 107 ...
Page 110
... NOTES: DS70139C-page 108 Preliminary © 2005 Microchip Technology Inc. ...
Page 111
... AN7 1000 AN8 1001 AN9 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The A/D module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 112
... A/D Result Buffer The module contains a 16-word dual port read only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 113
... 667 nsec (for V = 5V). Refer to the Electrical DD Specifications section for minimum T operating conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example 16-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. EXAMPLE 16-1: Minimum T ADCS<5:0> Therefore, Set ADCS< ...
Page 114
... FIGURE 16-2: 12-BIT A/D CONVERTER ANALOG INPUT MODEL ANx Rs C PIN VA Legend input capacitance PIN V = threshold voltage T I leakage = leakage current at the pin due to various junctions R = interconnect resistance sampling switch resistance sample/hold capacitance (from DAC) HOLD Note: C value depends on device package and is not tested. Effect of C PIN 16 ...
Page 115
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 16 ...
Page 116
... DS70139C-page 114 Preliminary © 2005 Microchip Technology Inc. ...
Page 117
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 115 ...
Page 118
... NOTES: DS70139C-page 116 Preliminary © 2005 Microchip Technology Inc. ...
Page 119
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 120
... TABLE 17-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 121
... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector Oscillator Start-up ...
Page 122
... Oscillator Configurations 17.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> configuration bits that select one of four oscillator groups, b) and FPR<4:0> configuration bits that select one of 15 oscillator choices within the primary group. ...
Page 123
... If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, then a PLL multiplier (respectively) is applied. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7.5 MHz. ...
Page 124
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, ...
Page 125
... Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected differentiates by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 126
... FIGURE 17-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 127
... Specifications in the specific device data sheet for BOR voltage limit specifications. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device configuration bit values (FOS<1:0> and FPR< ...
Page 128
... Table 17-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 17-5: ...
Page 129
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV; ...
Page 130
... Any interrupt that is individually enabled (using the cor- responding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The Sleep status bit in the RCON register is set upon wake-up. ...
Page 131
... Note: In the dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2005 Microchip Technology Inc. ...
Page 132
... DS70139C-page 130 Preliminary © 2005 Microchip Technology Inc. ...
Page 133
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 134
... All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
Page 135
... Y data space pre-fetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Wyd Y data space pre-fetch destination register for DSP instructions © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0..W15} ...
Page 136
... TABLE 18-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 137
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 138
... TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DISI DISI #lit14 30 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 31 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 34 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 35 EXCH EXCH Wns,Wnd 36 FBCL FBCL Ws,Wnd 37 FF1L FF1L ...
Page 139
... RRNC RRNC f RRNC f,WREG RRNC Ws,Wd © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 140
... TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 68 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 70 SETM SETM f SETM WREG SETM Ws 71 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 73 SUB SUB Acc ...
Page 141
... CAN ® - PowerSmart - Analog © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 142
... MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 143
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
Page 144
... PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program- mer or a PICSTART Plus development programmer ...
Page 145
... Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 146
... NOTES: DS70139C-page 144 Preliminary © 2005 Microchip Technology Inc. ...
Page 147
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) .................................... -0. ..........................................................................................................± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 148
... TABLE 20-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F201x-30I dsPIC30F301x-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F201x-20I dsPIC30F301x-20I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F201x-20E dsPIC30F301x-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: ∑ ...
Page 149
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C ...
Page 150
... TABLE 20-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC27 — — DC27a TBD — DC27b — — DC27c — — DC27d TBD — DC27e — — DC27f — — DC28 — — DC28a TBD — ...
Page 151
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 152
... TABLE 20-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. Idle Current (I ): Core OFF Clock ON Base Current IDLE DC47 — — DC47a TBD — DC47b — — DC47c — — DC47d TBD — DC47e — — DC47f — — DC48 — ...
Page 153
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C Units A -40° ...
Page 154
... TABLE 20-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power Down Current ( DC66 — — DC66a TBD — DC66b — — DC66c — — DC66d — — DC66e TBD — DC66f — — DC66g — — Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 155
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
Page 156
... TABLE 20-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKOUT ( Osc mode) V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKOUT ( Osc mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...
Page 157
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 20-2: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) RESET (due to BOR) © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — DD ...
Page 158
... TABLE 20-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. (2) BO10 V BOR Voltage BOR V transition high to DD low BO15 V BHYS Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. ...
Page 159
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin FIGURE 20-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T Operating voltage V range as described in DC Spec Section 20 ...
Page 160
... TABLE 20-14: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OS10 F External CLKIN Frequency OSC (External clocks allowed only in EC mode) Oscillator Frequency OS20 1/F OSC OSC OSC OS25 T Instruction Cycle Time CY (2) OS30 TosL, External Clock in (OSC1) TosH High or Low Time ...
Page 161
... EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle]. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T (1) (2) Min Typ Max (2) 4 — ...
Page 162
... TABLE 20-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Param Characteristic No. Internal FRC Accuracy @ FRC Freq = 7.37 MHz FRC FRC with x4 PLL FRC with x8 PLL FRC with x16 PLL Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. ...
Page 163
... Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 20-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. LPRC @ Freq = 512 kHz F20 F21 Note 1: Frequency at 25°C and 5V. 2: Change of LPRC frequency as V © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 -40°C T -40°C T Min Typ Max Units (1) TBD % TBD % ...
Page 164
... FIGURE 20-5: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 20-3 for load conditions. TABLE 20-20: CLKOUT AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 165
... V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 20-3 for load conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Preliminary SY20 SY13 DS70139C-page 163 ...
Page 166
... TABLE 20-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) SY11 T Power-up Timer Period PWRT SY12 T Power On Reset Delay POR SY13 T I/O Hi-impedance from MCLR ...
Page 167
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. FIGURE 20-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 20-3 for load conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C (1) ...
Page 168
... TABLE 20-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time TX TA15 T P TxCK Input Period Synchronous, TX OS60 Ft1 SOSC1/T1CK oscillator input frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) ...
Page 169
... TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer3 and Timer5 are Type C. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature Min Typ Synchronous, 0 — ...
Page 170
... FIGURE 20-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 20-3 for load conditions. TABLE 20-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
Page 171
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 172
... FIGURE 20-12: DCI MODULE (MULTICHANNEL, I CSCK (SCKE = 1) CSCK (SCKE = 0) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 20-3 for load conditions. DS70139C-page 170 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 ...
Page 173
... The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 174
... FIGURE 20-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 SYNC (COFS) CS80 MSb LSb SDO (CSDO) MSb IN SDI (CSDI) CS65 CS66 TABLE 20-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. CS60 T BIT_CLK Low Time ...
Page 175
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP20 BIT14 - - - - - -1 MSb SP30 BIT14 - - - -1 Standard Operating Conditions: 2 ...
Page 176
... FIGURE 20-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) MSb SDO X SP40 SP30,SP31 SDI X MSb IN SP41 Note: Refer to Figure 20-3 for load conditions. TABLE 20-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param ...
Page 177
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP72 MSb BIT14 - - - - - -1 SP30,SP31 ...
Page 178
... FIGURE 20-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. DS70139C-page 176 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb ...
Page 179
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
Page 180
... FIGURE 20-18 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 20-3 for load conditions. 2 FIGURE 20-19 BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. ...
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... BRG is the value of the I C Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™ the dsPIC30F Family Reference Manual. 2: Maximum pin capacitance = 10 pF for all I © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
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... FIGURE 20-20 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS30 SDA Start Condition 2 FIGURE 20-21 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70139C-page 180 IS33 IS11 IS10 IS26 IS25 IS40 Preliminary ...
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... IS45 T : Bus Free Time BF SDA IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° Min Max 100 kHz mode 4.7 — ...
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... FIGURE 20-22: CAN MODULE I/O TIMING CHARACTERISTICS C T Pin X X Old Value (output Pin X X (input) TABLE 20-37: CAN MODULE I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TioF CA10 Port Output Fall Time CA11 TioR Port Output Rise Time CA20 ...
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... ERR AD23A G Gain Error ERR Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C Min. Typ Max ...
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... TABLE 20-38: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param Symbol Characteristic No. AD24 E Offset Error OFF AD24A E Offset Error OFF (1) AD25 — Monotonicity AD26 CMRR Common-Mode Rejection AD27 PSRR Power Supply Rejection Ratio AD28 CTLK Channel to Channel Crosstalk AD30 THD Total Harmonic Distortion ...
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... Family Reference Manual , Section 18. T SAMP 3 - Software clears ADCON. SAMP to start conversion Sampling ends, conversion sequence starts Convert bit 11 Convert bit 10 Convert bit Convert bit One T for end of conversion. AD © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 AD55 Confidential DS70139C-page 185 ...
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... TABLE 20-39: 12-BIT A/D CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. AD50 T A/D Clock Period AD AD51 t A/D Internal RC Oscillator Period RC AD55 t Conversion Time CONV AD56 F Throughput Rate CNV AD57 T Sampling Time SAMP AD60 t Conversion Start from Sample PCS Trigger AD61 ...
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... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 e 30I/SO 0510017 Example dsPIC30F2012 30I/SP Preliminary ...
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... Package Marking Information (Continued) 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139C-page 188 Example dsPIC30F3013 e 30I/SO 0510017 Example 30F2011 e 30I/MM 3 0510017 Example dsPIC 30F3013 e 30I/ML 3 0510017 Preliminary © ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units INCHES* MIN NOM ...
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... Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...
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... Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units INCHES* MIN NOM MAX ...
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... Plastic Small Outline - Wide, 300 mil Body (SOIC Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom Drawing No ...
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... Pitch Overall Height Standoff Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length *Controlling Parameter Notes: JEDEC equivalent: MO-220 Drawing No. C04-124 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED METAL PAD OPTIONAL ALTERNATE INDEX INDEX BOTTOM VIEW ...
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... Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) DS70139C-page 194 Preliminary © 2005 Microchip Technology Inc. ...
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... Modifier Values Table ................................................. 45 Sequence Table (16-Entry)......................................... 45 Block Diagrams 12-bit A/D Functional ................................................ 109 16-bit Timer1 Module .................................................. 71 16-bit Timer2............................................................... 77 16-bit Timer3............................................................... 77 32-bit Timer2/3............................................................ 76 DSP Engine ................................................................ 22 dsPIC30F2011 ............................................................ 10 dsPIC30F2012 ............................................................ 11 dsPIC30F3013 ............................................................ 13 External Power-on Reset Circuit............................... 125 2 I C............................................................................... 94 Input Capture Mode .................................................... 81 © 2005 Microchip Technology Inc. ...
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... Erasing, Word ............................................................. 54 Protection Against Spurious Write .............................. 56 Reading....................................................................... 53 Write Verify ................................................................. 56 Writing ......................................................................... 55 Writing, Block .............................................................. 55 Writing, Word .............................................................. 55 DC Characteristics ............................................................ 145 BOR .......................................................................... 156 Brown-out Reset ....................................................... 155 I/O Pin Input Specifications ....................................... 153 I/O Pin Output Specifications .................................... 154 Idle Current (I ) .................................................... 149 IDLE Low-Voltage Detect................................................... 154 LVDL ......................................................................... 155 Operating Current (I ) ...
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... Port Write/Read Example ................................................... 58 PORTB Register Map for dsPIC30F2011/3012 ....................... 59 Register Map for dsPIC30F2012/3013 ....................... 59 PORTC Register Map for dsPIC30F2011/2012/3012/3013 ..... 59 PORTD Register Map for dsPIC30F2011/3012 ....................... 59 Register Map for dsPIC30F2012/3013 ....................... 60 PORTF Register Map for dsPIC30F2012/3013 ....................... 60 Power Saving Modes........................................................ 127 Idle............................................................................ 128 Sleep ........................................................................ 127 Sleep and Idle........................................................... 117 ...
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... Programmer’s Model........................................................... 18 Diagram ...................................................................... 19 Programming Operations .................................................... 49 Algorithm for Program Flash ....................................... 49 Erasing a Row of Program Memory ............................ 49 Initiating the Programming Sequence ......................... 50 Loading Write Latches ................................................ 50 Protection Against Accidental Writes to OSCCON ........... 122 R Reset......................................................................... 117, 123 BOR, Programmable................................................. 125 Brown-out Reset (BOR) ............................................ 117 Oscillator Start-up Timer (OST) ................................ 117 POR Operating without FSCM and PWRT ...